Patents by Inventor Hiroshi Kanemaru

Hiroshi Kanemaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120870
    Abstract: An abnormality diagnosis device includes: a feature quantity calculation unit which calculates a plurality of feature quantities from the time-series data of the current values; an operation mode determination unit which determines an operation mode of a compressor on the basis of the load torque and the drive frequency; a feature quantity distribution generation unit which generates a feature quantity distribution from values of the plurality of feature quantities; a reference region generation unit which generates a reference region on the basis of the feature quantity distribution that is obtained in a normal case; and a determination unit which compares the feature quantity distribution that is obtained during an abnormality diagnosis and the reference region corresponding to the operation mode that is applied during the abnormality diagnosis, to determine whether an abnormality is present or absent in either of the compressor and the electric motor.
    Type: Application
    Filed: April 8, 2021
    Publication date: April 11, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroshi INOUE, Ken HIRAKIDA, Makoto KANEMARU, Takaharu NAKAMURA
  • JIG
    Publication number: 20230115616
    Abstract: Provided is a jig which assists in the adhesion of a thin-film sheet to an adhesion target surface (skin etc.), and which can easily adhere the thin-film sheet to the adhesion target surface. The jig includes: a base part having a first surface; and a porous hydrophilic film that is adhered to the first surface and has fine pores with a predetermined porosity, wherein the porosity is 35% to 55% inclusive. The hardness of the base part is preferably 4-20 inclusive. In addition, it is preferable that the base part and the hydrophilic film have transparency.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 13, 2023
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hiroshi KANEMARU, Mari UEDA, Sachiko TAKESHITA
  • Patent number: 11284696
    Abstract: A thin film affixing device used to affix a thin film to an adherend surface, such as the face of a user, is provided. The thin film affixing device is configured to include a main portion having a first surface and a second surface, where the first surface has a temporary adherend portion that allows the thin film to be temporarily attached thereto, a holding member that holds the main portion so that the first side is viewable from the second side through the main portion and the temporary adherend portion is capable of pressing against the adherend surface, and a transparent hydrophilic layer formed on the first surface of the main portion so as to serve as the temporary adherend portion.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: March 29, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayo Shinoda, Hiroshi Kanemaru, Kazuma Tsujita, Takao Kajima
  • Publication number: 20190200732
    Abstract: A thin film application device used to apply a thin film on an applied face of an application object includes a frame mountable to the application object, and a thin film holding member, that has a tentative application portion to which the thin film can be tentatively applied to a side face facing the applied face in use, and that is supported by the frame so that the tentative application portion can be pressed against the applied face, and that is detachably mountable to the frame.
    Type: Application
    Filed: March 12, 2019
    Publication date: July 4, 2019
    Inventors: MASAYO SHINODA, KAZUMA TSUJITA, HIROSHI KANEMARU, TAKASHI SHIGA
  • Publication number: 20190200726
    Abstract: A thin film affixing device used to affix a thin film to an adherend surface, such as the face of a user, is provided. The thin film affixing device is configured to include a main portion having a first surface and a second surface, where the first surface has a temporary adherend portion that allows the thin film to be temporarily attached thereto, a holding member that holds the main portion so that the first side is viewable from the second side through the main portion and the temporary adherend portion is capable of pressing against the adherend surface, and a transparent hydrophilic layer formed on the first surface of the main portion so as to serve as the temporary adherend portion.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 4, 2019
    Inventors: MASAYO SHINODA, HIROSHI KANEMARU, KAZUMA TSUJITA, TAKAO KAJIMA
  • Patent number: 8534318
    Abstract: To provide a water spouting device capable of switching between spouting and stopping, flow volume adjustment, and spouted water temperature adjustment with a single operating portion. The present invention is a water faucet device (1) furnished with a flow volume adjustment function and a temperature adjustment function, including: an operating portion (6) capable of being pressed and rotated by a user; and flow volume/temperature adjustment means (10), whereby in a stopped water state, spouting is commenced when the operating portion of this flow volume/temperature adjustment means is pressed; in a spouting state, spouted water flow volume is changed when the operating portion is pressed continuously for a predetermined long-press determining time; and water flow is stopped when pressing of the operating portion ceases in less than the long-press determining time.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: September 17, 2013
    Assignee: Toto Ltd.
    Inventors: Hiroshi Kanemaru, Kenichi Aoyagi, Masato Yamahigashi, Masateru Miyazaki, Tsuyoshi Miura
  • Patent number: 8317110
    Abstract: A water-and-hot-water mixing device includes a mixing valve unit which mixes hot water and water and discharges mixed water therefrom, an operation part which sets a predetermined temperature, a mixed water thermistor which detects a temperature of mixed water, a hot-water thermistor which detects a temperature of hot water supplied to the mixing valve unit, and a controller which performs a feedback control of a discharge water temperature by controlling the mixing valve unit. The controller starts the feedback control when the controller determines that a change amount of the temperature of the hot water per unit time detected by the hot-water thermistor is not more than a fixed value and the temperature of the hot water detected by the hot-water thermistor is not lower than the predetermined temperature.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: November 27, 2012
    Assignee: Toto Ltd.
    Inventors: Kenichi Aoyagi, Hiroshi Kanemaru, Tsuyoshi Miura, Masayuki Oba
  • Publication number: 20110005619
    Abstract: To provide a water faucet device capable of easy grasp of setting states, without enlarging the size of the display portion. The present invention is a water faucet device (1) furnished with a flow setting function or temperature setting function; whereby the water faucet device has an operating portion (6) for controlling the water faucet device; a spout portion (2) forming a water discharge port; a light injecting portion (42), disposed at the base of the spout portion or the operating portion so as to be adjacent to the attaching surface at which the spout portion or the control portion are attached, for shining light onto the attaching surface; and display means (26) for displaying flow setting values or temperature setting values by varying the illumination range (46) formed on the attaching surface by the light illuminated from the light injecting portion.
    Type: Application
    Filed: September 20, 2010
    Publication date: January 13, 2011
    Applicant: TOTO LTD.
    Inventors: Hiroshi KANEMARU, Kenichi AOYAGI, Masato YAMAHIGASHI, Masateru MIYAZAKI, Tsuyoshi MIURA
  • Publication number: 20110005627
    Abstract: To provide a water spouting device capable of switching between spouting and stopping, flow volume adjustment, and spouted water temperature adjustment with a single operating portion. The present invention is a water faucet device (1) furnished with a flow volume adjustment function and a temperature adjustment function, including: an operating portion (6) capable of being pressed and rotated by a user; and flow volume/temperature adjustment means (10), whereby in a stopped water state, spouting is commenced when the operating portion of this flow volume/temperature adjustment means is pressed; in a spouting state, spouted water flow volume is changed when the operating portion is pressed continuously for a predetermined long-press determining time; and water flow is stopped when pressing of the operating portion ceases in less than the long-press determining time.
    Type: Application
    Filed: September 20, 2010
    Publication date: January 13, 2011
    Applicant: TOTO LTD.
    Inventors: Hiroshi KANEMARU, Kenichi AOYAGI, Masato YAMAHIGASHI, Masateru MIYAZAKI, Tsuyoshi MIURA
  • Patent number: 7723817
    Abstract: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface. This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.
    Type: Grant
    Filed: May 29, 2006
    Date of Patent: May 25, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Hiroshi Kanemaru, Naoki Kumagai, Yuichi Harada, Yoshihiro Ikura, Yoshiaki Minoya
  • Publication number: 20100078491
    Abstract: A water-and-hot-water mixing device includes a mixing valve unit which mixes hot water and water and discharges mixed water therefrom, an operation part which sets a predetermined temperature, a mixed water thermistor which detects a temperature of mixed water, a hot-water thermistor which detects a temperature of hot water supplied to the mixing valve unit, and a controller which performs a feedback control of a discharge water temperature by controlling the mixing valve unit. The controller starts the feedback control when the controller determines that a change amount of the temperature of the hot water per unit time detected by the hot-water thermistor is not more than a fixed value and the temperature of the hot water detected by the hot-water thermistor is not lower than the predetermined temperature.
    Type: Application
    Filed: September 23, 2009
    Publication date: April 1, 2010
    Applicant: TOTO LTD.
    Inventors: Kenichi AOYAGI, Hiroshi KANEMARU, Tsuyoshi MIURA, Masayuki OBA
  • Patent number: 7602022
    Abstract: To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the impurity density gradient in the vicinity of the strong electric field region are optimized. During avalanche breakdown, a depletion layer is formed across the entire high resistivity region, and its average electric field is kept to ½ or more of the maximum electric field intensity. The density gradients (the depths and impurity densities) of a p+ region and of an n+ region that form a p-n junction of the diode are controlled so that the density gradient in the neighborhood of the high resistivity region does not have negative resistance with respect to increase of the avalanche current.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: October 13, 2009
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Naoki Kumagai, Hiroshi Kanemaru, Yuiichi Harada, Yoshihiro Ikura, Ryuu Saitou
  • Patent number: 7436024
    Abstract: A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: October 14, 2008
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Hiroshi Kanemaru, Yoshihiro Ikura, Ryuu Saitou
  • Publication number: 20070029636
    Abstract: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.
    Type: Application
    Filed: May 29, 2006
    Publication date: February 8, 2007
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Hiroshi Kanemaru, Naoki Kumagai, Yuichi Harada, Yoshihiro Ikura, Yoshiaki Minoya
  • Publication number: 20060231836
    Abstract: To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the impurity density gradient in the vicinity of the strong electric field region are optimized. During avalanche breakdown, a depletion layer is formed across the entire high resistivity region, and its average electric field is kept to ½ or more of the maximum electric field intensity. The density gradients (the depths and impurity densities) of a p+ region and of an n+ region that form a p-n junction of the diode are controlled so that the density gradient in the neighborhood of the high resistivity region does not have negative resistance with respect to increase of the avalanche current.
    Type: Application
    Filed: March 14, 2006
    Publication date: October 19, 2006
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Naoki Kumagai, Hiroshi Kanemaru, Yuiichi Harada, Yoshihiro Ikura, Ryuu Saitou
  • Patent number: 7098488
    Abstract: An IGBT having a trench gate structure is disclosed which generates decreased noise at switching and displays superiority in saturation voltage to turn-off loss characteristics (trade-off characteristics). In a part of a region on an emitter side surface interposed between trench gates, a sub well region is provided, which is connected to an emitter electrode through diodes. When the IGBT is in a turned-on state, the diodes are brought into a non-conduction state to isolate the sub well region from the emitter electrode, by which carriers are accumulated. When the IGBT is in a turned-off state, the diodes are brought into a conduction state to electrically connect the sub well region to the emitter electrode, by which carriers are discharged at a high speed. In an early stage of turning-on of the IGBT, capacitance of a portion of the gate facing the sub well region is converted to gate-emitter capacitance to thereby reduce gate-collector capacitance, by which electromagnetic noise at switching is reduced.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: August 29, 2006
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Koh Yoshikawa, Katsunori Ueno, Hiroshi Kanemaru
  • Publication number: 20060027863
    Abstract: A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.
    Type: Application
    Filed: August 3, 2005
    Publication date: February 9, 2006
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Hiroshi Kanemaru, Yoshihiro Ikura, Ryuu Saitou
  • Publication number: 20050045945
    Abstract: An IGBT having a trench gate structure is disclosed which generates decreased noise at switching and displays superiority in saturation voltage to turn-off loss characteristics (trade-off characteristics). In a part of a region on an emitter side surface interposed between trench gates, a sub well region is provided, which is connected to an emitter electrode through diodes. When the IGBT is in a turned-on state, the diodes are brought into a non-conduction state to isolate the sub well region from the emitter electrode, by which carriers are accumulated. When the IGBT is in a turned-off state, the diodes are brought into a conduction state to electrically connect the sub well region to the emitter electrode, by which carriers are discharged at a high speed. In an early stage of turning-on of the IGBT, capacitance of a portion of the gate facing the sub well region is converted to gate-emitter capacitance to thereby reduce gate-collector capacitance, by which electromagnetic noise at switching is reduced.
    Type: Application
    Filed: May 5, 2004
    Publication date: March 3, 2005
    Inventors: Koh Yoshikawa, Katsunori Ueno, Hiroshi Kanemaru
  • Patent number: 6483164
    Abstract: A Schottky electrode is formed of an alloy, which is composed of two or more kinds of metal materials in combinations that provide different Schottky barrier heights with respect to a semiconductor and that form no intermetallic compound.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: November 19, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiroshi Kanemaru, Shinji Ogino
  • Patent number: 5502003
    Abstract: Reciprocal diffusion is prevented in a SiC electronic device by interposing an intermediate layer composed of W or a W-Si alloy rather than forming the Ni electrode directly on a SiC base, providing a stable electrode for which the contact resistance does not increase even when high temperatures are maintained. Bonding is facilitated when Au layer is formed on top of the Ni layer.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: March 26, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shinji Ogino, Tatsuo Urushidani, Hiroshi Kanemaru