Abstract: A power transmitting and receiving system includes a power receiving device including a power receiving coil, and a power transmission device including power transmission coils arranged in a line, a power transmission circuit, and control circuitry. The control circuitry switches an electrical connection between the power transmission circuit and each power transmission coil, detects a relative position between the power receiving coil and each power transmission coil, selects adjacent power transmission coils based on the relative position, and causes the power transmission circuit to supply AC power to the selected power transmission coils. In an array direction of the power transmission coils, width Dwt of each power transmission coil is shorter than width Dwr of the power receiving coil. In a direction perpendicular to the array direction, width Dlt of each power transmission coil is equal to or longer than width Dlr of the power receiving coil.

Abstract: A power transmission device includes power transmission coils arranged in a line, a power transmission circuit connected to the power transmission coils, and control circuitry that switches an electrical connection between the power transmission circuit and each power transmission coil, detects a relative position between the power receiving coil and each power transmission coil, selects two or more power transmission coils adjacent to each other based on the detected relative position, and causes the power transmission circuit to supply the AC power to the selected two or more power transmission coils. In a direction perpendicular to an array direction of the power transmission coils, width Dlt of each power transmission coil is equal to or longer than width Dlr of the power receiving coil. In the array direction, width Dwt of each power transmission coil is shorter than width Dwr of the power receiving coil and satisfies 0.2?Dwt/Dwr.

Abstract: The semiconductor storage device of an embodiment includes a first conductive layer, a stack disposed above the first conductive layer and including a plurality of second conductive layers in a first direction, and a columnar body that extends in the first direction through the stack, and includes a semiconductor layer and a charge storage film provided between the plurality of conductive layers and the semiconductor layer. A first conductive layer out of the plurality of conductive layers is connected to the semiconductor layer, and the semiconductor layer includes a first region in which a concentration of an n-type impurity is higher than a concentration of a p-type impurity, a second region in which a concentration of a p-type impurity is higher than a concentration of an n-type impurity, and a third region contacted to the first conductive layer and disposed closer to the first region than the second region in the first direction.

Abstract: A power transmitting and receiving system includes a power receiving device including a power receiving coil, and a power transmission device including power transmission coils arranged in a line, a power transmission circuit, and control circuitry. The control circuitry switches an electrical connection between the power transmission circuit and each power transmission coil, detects a relative position between the power receiving coil and each power transmission coil, selects adjacent power transmission coils based on the relative position, and causes the power transmission circuit to supply AC power to the selected power transmission coils. In an array direction of the power transmission coils, width Dwt of each power transmission coil is shorter than width Dwr of the power receiving coil. In a direction perpendicular to the array direction, width Dlt of each power transmission coil is equal to or longer than width Dlr of the power receiving coil.

Abstract: A power transmission device includes power transmission coils arranged in a line, a power transmission circuit connected to the power transmission coils, and control circuitry that switches an electrical connection between the power transmission circuit and each power transmission coil, detects a relative position between the power receiving coil and each power transmission coil, selects two or more power transmission coils adjacent to each other based on the detected relative position, and causes the power transmission circuit to supply the AC power to the selected two or more power transmission coils. In a direction perpendicular to an array direction of the power transmission coils, width Dlt of each power transmission coil is equal to or longer than width Dlr of the power receiving coil. In the array direction, width Dwt of each power transmission coil is shorter than width Dwr of the power receiving coil and satisfies 0.2?Dwt/Dwr.

Abstract: A power transmission device includes power transmission coils arranged in a line, a power transmission circuit connected to the power transmission coils, and control circuitry that switches an electrical connection between the power transmission circuit and each power transmission coil, detects a relative position between the power receiving coil and each power transmission coil, selects two or more power transmission coils adjacent to each other based on the detected relative position, and causes the power transmission circuit to supply the AC power to the selected two or more power transmission coils. In an array direction of the power transmission coils, a width Dwt of each power transmission coil is shorter than a width Dwr of the power receiving coil. In a direction perpendicular to the array direction, a width Dlt of each power transmission coil is equal to or longer than a width Dlr of the power receiving coil.

Abstract: According to one embodiment, a semiconductor memory device includes a first wiring layer above a first semiconductor layer in a first direction and a second wiring layer above the first semiconductor layer and spaced from the first wiring layer in a second direction. A first memory pillar extends through the first wiring layer. A second memory pillar extends through the second wiring layer. A member is between the first and second wiring layers in the second direction and includes a first conductor contacting the first semiconductor layer, a first insulator between the wiring layers and the first conductor, and a plurality of second insulators arranged along a third direction and between the first conductor and the first semiconductor layer in the first direction.

Abstract: Generally, the current threshold value is set as a fixed value. Therefore, even in a case where an abnormality occurs in the load and the resistance value is small, when the power supply voltage applied to the load is low, the current value is also low, and falls below the threshold value, and there is a possibility that the overcurrent is not detected. In the present invention, by providing a second detection means that detects a load abnormality by calculating the resistance value of the load from information of the power supply voltage applied to the load, in addition to a first detection means that detects an overcurrent state that indicates the load abnormality using only current value information, it is possible to detect an overcurrent indicating an abnormality of the load even when the power supply voltage applied to the load is low.

Abstract: The present invention provides an infusion preparation that is inhibited from generation of unwanted insoluble matter after mixing of two liquids of the infusion preparation in long-term storage. More specifically, the present invention provides an infusion preparation comprising two chambers separated by a communicably openable partition, a first chamber containing a first-chamber infusion comprising a fat emulsion and further comprising at least one member selected from the group consisting of amino acids that have a buffer action, divalent organic acids, and trivalent organic acids, a second chamber containing a second-chamber infusion comprising an amino acid and at least calcium as an electrolyte, wherein a total concentration of the amino acids that have a buffer action, divalent organic acids, and trivalent organic acids in the first-chamber infusion is 0.15 to 0.5 g/L, and a mixture of the first- and second-chamber infusions has a pH of 6.

Abstract: The semiconductor storage device of an embodiment includes a first conductive layer, a stack disposed above the first conductive layer and including a plurality of second conductive layers in a first direction, and a columnar body that extends in the first direction through the stack, and includes a semiconductor layer and a charge storage film provided between the plurality of conductive layers and the semiconductor layer. A first conductive layer out of the plurality of conductive layers is connected to the semiconductor layer, and the semiconductor layer includes a first region in which a concentration of an n-type impurity is higher than a concentration of a p-type impurity, a second region in which a concentration of a p-type impurity is higher than a concentration of an n-type impurity, and a third region contacted to the first conductive layer and disposed closer to the first region than the second region in the first direction.

Abstract: A tire comprising: a tread portion contacting a road surface; a groove provided in the tread portion; and a plurality of projections provided at groove side walls of the groove, wherein the plurality of projections are provided at least at any position within a region of from 40 to 60% of a groove depth of the groove side walls, and wherein, as seen in a cross-section in a width direction of the groove, an apex of the projection is positioned further toward a tread surface side of the tread portion than a width direction central portion of a base of the projection.

Abstract: The semiconductor storage device of an embodiment includes a first conductive layer, a stack disposed above the first conductive layer and including a plurality of second conductive layers in a first direction, and a columnar body that extends in the first direction through the stack, and includes a semiconductor layer and a charge storage film provided between the plurality of conductive layers and the semiconductor layer. A first conductive layer out of the plurality of conductive layers is connected to the semiconductor layer, and the semiconductor layer includes a first region in which a concentration of an n-type impurity is higher than a concentration of a p-type impurity, a second region in which a concentration of a p-type impurity is higher than a concentration of an n-type impurity, and a third region contacted to the first conductive layer and disposed closer to the first region than the second region in the first direction.

Abstract: A semiconductor memory device includes: a stack having conductive layers and insulating layers, the conductive layers including a first select gate line connected to a gate of a first select transistor, a word line provided above the first select gate line and connected to a gate of a memory transistor, and a second select gate line provided above the word line and connected to a gate of a second select transistor; a core insulating layer having a top surface lower than a top surface of the second select gate line; a semiconductor layer having a first semiconductor part having channel formation regions of the transistors and a second semiconductor part on the top surface of the core insulating layer; and a memory layer between the semiconductor layer and the stack. The first semiconductor part has an impurity semiconductor region containing an impurity and overlapping with the second select gate line.

Abstract: This method for manufacturing a solar cell module comprises a step for applying an adhesive to a first adhesion region so that the first adhesion region and a second adhesion region are disposed alternately on a light receiving surface of a solar cell along a first direction, and a step for arranging a light receiving surface-side wiring material along the first direction on the light receiving surface side of the solar cell to which the adhesive has been applied. The step for arranging the light receiving surface-side wiring material comprises arranging the light receiving surface-side wiring material, in the first adhesion region and the second adhesion region of the solar cell so that, in a state in which a first holder is in contact with the holding region of the light receiving surface-side wiring material, the second adhesion region and the holding region overlap each other.

Abstract: A semiconductor storage device includes a plurality of memory cell transistors, a first wiring electrically connected to the plurality of memory cell transistors, and an erasing circuitry. The erasing circuitry is configured to erase data stored in the memory cell transistors by applying a first voltage to the first wiring, and apply the first voltage such that the first voltage rises to a first value, then falls from the first value to a second value, and is then maintained at the second value.

Abstract: There is provided a method of inducing differentiation of bone marrow stromal cells to neural cells or skeletal muscle cells by introduction of a Notch gene. Specifically, the invention provides a method of inducing differentiation of bone marrow stromal cells to neural cells or skeletal muscle cells in vitro, which method comprises introducing a Notch gene and/or a Notch signaling related gene into the cells, wherein the finally obtained differentiated cells are the result of cell division of the bone marrow stromal cells into which the Notch gene and/or Notch signaling related gene have been introduced. The invention also provides a method of inducing further differentiation of the differentiation-induced neural cells to dopaminergic neurons or acetylcholinergic neurons. The invention yet further provides a treatment method for neurodegenerative and skeletal muscle degenerative diseases which employs neural precursor cells, neural cells or skeletal muscle cells produced by the method of the invention.

Abstract: Provided is an anti oxidant supply composition that enables replenishment of a rubber article with anti oxidant without taking a long time. An anti oxidant supply composition comprises: a base material and 5 mass % or more of anti oxidant, wherein a solubility parameter (SP value) of the base material is less than 7.8 (cal/cm3)1/2.

Abstract: The semiconductor storage device of an embodiment includes a first conductive layer, a stack disposed above the first conductive layer and including a plurality of second conductive layers in a first direction, and a columnar body that extends in the first direction through the stack, and includes a semiconductor layer and a charge storage film provided between the plurality of conductive layers and the semiconductor layer. A first conductive layer out of the plurality of conductive layers is connected to the semiconductor layer, and the semiconductor layer includes a first region in which a concentration of an n-type impurity is higher than a concentration of a p-type impurity, a second region in which a concentration of a p-type impurity is higher than a concentration of an n-type impurity, and a third region contacted to the first conductive layer and disposed closer to the first region than the second region in the first direction.

Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.

Abstract: A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.