Patents by Inventor Hiroshi Kariyazono

Hiroshi Kariyazono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5723910
    Abstract: A first Al wire is connected to a gate electrode. On the first Al wire, an insulating film is provided. In the insulating film, an opening with a large cross-sectional area is made so as to correspond to the first Al wire. In the periphery of the opening, the insulating film is etched by RIE to make an opening. In the central area, the insulating film is etched by wet etching to make an opening. Inside the opening thus made, a second Al wire is formed. The second Al wire is connected to the first Al wire inside the opening. When the opening is made, the number of electrons trapped in the gate oxide film is small because the area etched by RIE is small. Since RIE etches the first Al wire deeper than wet etching, recesses are made around the first Al wire located inside the opening. The first and second Al wires are connected to each other via the recesses.
    Type: Grant
    Filed: January 19, 1996
    Date of Patent: March 3, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kariyazono, Katsu Honna
  • Patent number: 5719432
    Abstract: An N-type buried region formed in the surface area of a semiconductor substrate is electrically connected to an N-type collector region formed in an epitaxial silicon layer on the semiconductor substrate. A P-type buried region is formed to overlap part of the N-type buried region. The P-type buried region is thick in the upward and downward directions of the N-type buried region. One end portion of the P-type buried region is electrically connected to a P-type base region and the other end portion thereof is electrically connected to a base region formed in the surface area of the semiconductor layer. The base region is applied with a base potential from the base region via the buried region. An N-type emitter region is formed in the base region. The N-type buried region and the P-type buried region are simultaneously formed by use of a difference between the diffusion coefficients of impurity.
    Type: Grant
    Filed: June 25, 1996
    Date of Patent: February 17, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kariyazono, Katsu Honna
  • Patent number: 5525544
    Abstract: A first Al wire is connected to a gate electrode. On the first Al wire, an insulating film is provided. In the insulating film, an opening with a large cross-sectional area is made so as to correspond to the first Al wire. In the periphery of the opening, the insulating film is etched by RIE to make an opening. In the central area, the insulating film is etched by wet etching to make an opening. Inside the opening thus made, a second Al wire is formed. The second Al wire is connected to the first Al wire inside the opening. When the opening is made, the number of electrons trapped in the gate oxide film is small because the area etched by RIE is small. Since RIE etches the first Al wire deeper than wet etching, recesses are made around the first Al wire located inside the opening. The first and second Al wires are connected to each other via the recesses.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: June 11, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kariyazono, Katsu Honna