Abstract: A memory system is connectable to a host device, and includes a nonvolatile memory, a signal line connected to the nonvolatile memory, and a memory controller. The memory controller is connected to the signal line, and repeatedly performs de-assertion and assertion of the signal line at a first frequency while transmitting or receiving data to or from the nonvolatile memory. The memory controller, in response to receiving a first command from the host, repeatedly performs the de-assertion and the assertion of the signal line at a second frequency lower than the first frequency while transmitting or receiving the data to or from the nonvolatile memory.

Abstract: A memory system is connectable to a host device, and includes a nonvolatile memory, a signal line connected to the nonvolatile memory, and a memory controller. The memory controller is connected to the signal line, and repeatedly performs de-assertion and assertion of the signal line at a first frequency while transmitting or receiving data to or from the nonvolatile memory. The memory controller, in response to receiving a first command from the host, repeatedly performs the de-assertion and the assertion of the signal line at a second frequency lower than the first frequency while transmitting or receiving the data to or from the nonvolatile memory.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.