Patents by Inventor Hiroshi Kawagoe

Hiroshi Kawagoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11024554
    Abstract: A wiring substrate includes an insulating substrate being square in plan view, the insulating substrate including one main surface with a recess, and the other main surface opposite to the one main surface, and external electrodes located on the other main surface of the insulating substrate. The external electrodes are arranged in a row in a peripheral section of the insulating substrate. In plan view, an area of one of the external electrodes located at a center of each side of the insulating substrate is larger than an area of one of the external electrodes located at an edge of the each side.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 1, 2021
    Assignee: KYOCERA CORPORATION
    Inventor: Hiroshi Kawagoe
  • Patent number: 10937707
    Abstract: A wiring substrate includes an insulating substrate that is square in plan view, the insulating substrate having one main surface with a recess and an other main surface opposite to the one main surface, and external electrodes located on the other main surface of the insulating substrate and in a peripheral section of the insulating substrate. The external electrodes include first external electrodes and second external electrodes. In plan view, the first external electrodes are located at corners of the insulating substrate, and the second external electrodes are interposed between the first external electrodes. Each of the first external electrodes has a smaller area and a larger width in a direction orthogonal to each side of the insulating substrate than each of the second external electrodes.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: March 2, 2021
    Assignee: Kyocera Corporation
    Inventor: Hiroshi Kawagoe
  • Publication number: 20200058568
    Abstract: A wiring substrate includes an insulating substrate that is square in plan view, the insulating substrate having one main surface with a recess and an other main surface opposite to the one main surface, and external electrodes located on the other main surface of the insulating substrate and in a peripheral section of the insulating substrate. The external electrodes include first external electrodes and second external electrodes. In plan view, the first external electrodes are located at corners of the insulating substrate, and the second external electrodes are interposed between the first external electrodes. Each of the first external electrodes has a smaller area and a larger width in a direction orthogonal to each side of the insulating substrate than each of the second external electrodes.
    Type: Application
    Filed: February 22, 2018
    Publication date: February 20, 2020
    Applicant: KYOCERA Corporation
    Inventor: Hiroshi KAWAGOE
  • Publication number: 20190378772
    Abstract: A wiring substrate includes an insulating substrate being square in plan view, the insulating substrate including one main surface with a recess, and the other main surface opposite to the one main surface, and external electrodes located on the other main surface of the insulating substrate. The external electrodes are arranged in a row in a peripheral section of the insulating substrate. In plan view, an area of one of the external electrodes located at a center of each side of the insulating substrate is larger than an area of one of the external electrodes located at an edge of the each side.
    Type: Application
    Filed: February 20, 2018
    Publication date: December 12, 2019
    Applicant: KYOCERA Corporation
    Inventor: Hiroshi KAWAGOE
  • Patent number: 10174914
    Abstract: A light-emitting-element mounting substrate according to the present invention includes a substrate, a mount portion for mounting a light emitting element on a main surface of the substrate, and a resin frame surrounding the mount portion in plan view and to be in contact with an encapsulant for encapsulating the light emitting element to be mounted. The resin frame includes a recess in a main surface thereof, the recess surrounding the mount portion in plan view.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: January 8, 2019
    Assignee: KYOCERA Corporation
    Inventors: Hiroshi Kawagoe, Masataka Yoshida
  • Patent number: 10165669
    Abstract: A wiring board comprises an insulating substrate; and a heat-transfer member disposed inside the insulating substrate. The insulating substrate comprises an upper surface and a recess formed in the upper surface, the upper surface including a first mounting region for a first electronic component, and a second mounting region for a second electronic component which is provided in the recess. The heat-transfer member is disposed inside the insulating substrate so as to overlap the first mounting region and the second mounting region as seen in a plan view, and, part of the heat-transfer member is exposed in the recess.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 25, 2018
    Assignee: KYOCERA Corporation
    Inventors: Hiroshi Kawagoe, Yasunori Suda
  • Publication number: 20180163954
    Abstract: A light-emitting-element mounting substrate according to the present invention includes a substrate, a mount portion for mounting a light emitting element on a main surface of the substrate, and a resin frame surrounding the mount portion in plan view and to be in contact with an encapsulant for encapsulating the light emitting element to be mounted. The resin frame includes a recess in a main surface thereof, the recess surrounding the mount portion in plan view.
    Type: Application
    Filed: August 22, 2016
    Publication date: June 14, 2018
    Applicant: KYOCERA Corporation
    Inventors: Hiroshi KAWAGOE, Masataka YOSHIDA
  • Patent number: 9596747
    Abstract: A wiring substrate in which a plating layer is sufficiently plated on a surface metal layer and which has an excellent reliability is provided. A wiring substrate includes an insulating base; a heat dissipation member disposed in the insulating base, the heat dissipation member partially exposed from the insulating base, the heat dissipation member containing Cu; a surface metal layer disposed on a surface of the insulating base, the surface metal layer contacting and covering the heat dissipation member, the surface metal layer containing Mo as a main component, the surface metal layer including a surface portion containing Cu; and a plating layer disposed on the surface metal layer, wherein Cu contained in the heat dissipation member and Cu contained in the surface portion are bonded to each other.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: March 14, 2017
    Assignee: KYOCERA CORPORATION
    Inventors: Hiroshi Kawagoe, Kazuhiko Yagi
  • Publication number: 20150334877
    Abstract: To improve the operation characteristics of an electronic component housed in a recess of an insulating substrate. A wiring board comprises an insulating substrate; and a heat-transfer member disposed inside the insulating substrate. The insulating substrate comprises an upper surface and a recess formed in the upper surface, the upper surface including a first mounting region for a first electronic component, and a second mounting region for a second electronic component which is provided in the recess. The heat-transfer member is disposed inside the insulating substrate so as to overlap the first mounting region and the second mounting region as seen in a plan view, and, part of the heat-transfer member is exposed in the recess.
    Type: Application
    Filed: December 22, 2011
    Publication date: November 19, 2015
    Inventors: Hiroshi KAWAGOE, Yasunori SUDA
  • Publication number: 20140196934
    Abstract: A wiring substrate in which a plating layer is sufficiently plated on a surface metal layer and which has an excellent reliability is provided. A wiring substrate includes an insulating base; a heat dissipation member disposed in the insulating base, the heat dissipation member partially exposed from the insulating base, the heat dissipation member containing Cu; a surface metal layer disposed on a surface of the insulating base, the surface metal layer contacting and covering the heat dissipation member, the surface metal layer containing Mo as a main component, the surface metal layer including a surface portion containing Cu; and a plating layer disposed on the surface metal layer, wherein Cu contained in the heat dissipation member and Cu contained in the surface portion are bonded to each other.
    Type: Application
    Filed: June 29, 2012
    Publication date: July 17, 2014
    Applicant: Kyocera Corporation
    Inventors: Hiroshi Kawagoe, Kazuhiko Yagi
  • Publication number: 20090033992
    Abstract: A printing apparatus includes a printing unit, a communication unit which receives a print job that requires user authentication, a RAM which stores the print job received by the communication unit, and a user interface which is operated to input authentication information with respect to the print job stored in the RAM. The apparatus includes a processor unit which detects a non-printable error that occurs in the printing unit during execution of the print job, sets treatment of the print job interrupted due to the error, performs the user authentication on the basis of the authentication information input by using the user interface for execution of the print job stored in the RAM, executes the print job when the user authentication is successful, and performs a process of subjecting the print job to the set treatment when the non-printable error is detected during the execution of the print job.
    Type: Application
    Filed: July 29, 2008
    Publication date: February 5, 2009
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Takashi Ogiwara, Hiroshi Kawagoe
  • Patent number: 7444111
    Abstract: An image forming apparatus, such as a copying machine is provided. In the device, a predetermined period of time is measured from when an operator has specified a desired size of paper through an operation panel. A duration is measured, during which a paper feed cassette accommodating the desired-size paper specified through the operation panel has been absent from a cassette loading section at a specified loading position. A determination is made as to whether or not an appropriate operational condition has been met by completing loading of a paper feed cassette accommodating the desired-size paper on the cassette loading section, provided that the duration has lasted for more than a certain period of time within the predetermined period of time. When it is determined that the appropriate operational condition has not been met, a warning indicative of the inappropriate operational condition is given through the operation panel.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: October 28, 2008
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventor: Hiroshi Kawagoe
  • Publication number: 20060204254
    Abstract: An image forming apparatus, such as a copying machine is provided. In the device, a predetermined period of time is measured from when an operator has specified a desired size of paper through an operation panel. A duration is measured, during which a paper feed cassette accommodating the desired-size paper specified through the operation panel has been absent from a cassette loading section at a specified loading position. A determination is made as to whether or not an appropriate operational condition has been met by completing loading of a paper feed cassette accommodating the desired-size paper on the cassette loading section, provided that the duration has lasted for more than a certain period of time within the predetermined period of time. When it is determined that the appropriate operational condition has not been met, a warning indicative of the inappropriate operational condition is given through the operation panel.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 14, 2006
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventor: Hiroshi Kawagoe