Patents by Inventor Hiroshi Kawaguchi
Hiroshi Kawaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180261434Abstract: In an insulating structure which insulates an electrode provided inside a vacuum region of an ion implanter from another member and supports the electrode, a first insulating member supports the electrode. A second insulating member is fitted to the first insulating member to suppress deposition of contamination particles to the first insulating member. The second insulating member is formed of a material having a hardness lower than that of the first insulating member. A Vickers hardness of an outer surface of the second insulating member is 5 GPa or less. Bending strength of the second insulating member is 100 MPa or less. The second insulating member is formed of a material including at least one of boron nitride, a porous ceramic, and a resin.Type: ApplicationFiled: March 12, 2018Publication date: September 13, 2018Inventors: Hiroshi Kawaguchi, Yuuji Ishida
-
Publication number: 20180250561Abstract: Golf clubs and golf club heads having a weight member that is configurable in multiple positions to alter the performance characteristics of the golf club head are presented. In some examples, the weight member may be arranged in a sole of the golf club head and may include ends having different weighting characteristics. For instance, one end may be heavier or denser than another end of the weight member. The difference in weight characteristics may be due to different materials used to form the different ends, different construction of the ends, and the like. The position of the weight member may be adjusted to alter the performance characteristics of the golf club head. For instance, the weight member may be removed and rotated to position a heavier end where a lighter end was previously positioned.Type: ApplicationFiled: May 4, 2018Publication date: September 6, 2018Inventors: Andrew G.V. Oldknow, James S. Thomas, Hiroshi Kawaguchi, Robert Boyd
-
Publication number: 20180254166Abstract: An ion generator includes an arc chamber which has a plasma generating region therein, a cathode configured to emit a thermoelectron toward the plasma generating region, a repeller which faces the cathode in an axial direction in a state where the plasma generating region is interposed between the cathode and the repeller, and a cage which is disposed to partially surround the plasma generating region at a position between an inner surface of the arc chamber and the plasma generating region.Type: ApplicationFiled: March 5, 2018Publication date: September 6, 2018Inventor: Hiroshi Kawaguchi
-
Publication number: 20180250562Abstract: A ball striking device, such as a golf club head, has a head that includes a face configured for striking a ball and a body connected to the face, the body being adapted for connection of a shaft proximate a heel thereof The face has a thickened portion including an annular tapered area that tapers in thickness between an upper boundary and a lower boundary and encloses an elevated area bounded by the upper boundary. The upper and/or lower boundary defines a shape having two lobes, each with an outer edge with a convex profile, and a connecting portion extending between the lobes, such that the connecting portion is defined by two outer edges extending between the outer edges of the lobes, wherein at least one of the outer edges of the connecting portion has a concave outer profile.Type: ApplicationFiled: May 7, 2018Publication date: September 6, 2018Inventors: Robert M. Boyd, Jeremy N. Snyder, Hiroshi Kawaguchi, James S. Thomas, Raymond J. Sander, Rick S. Wahlin, Akira Shimozuuma
-
Patent number: 10050142Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: GrantFiled: October 20, 2017Date of Patent: August 14, 2018Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi
-
Patent number: 9999811Abstract: A ball striking device, such as a golf club head, has a head that includes a face configured for striking a ball and a body connected to the face, the body being adapted for connection of a shaft proximate a heel thereof. The face has a thickened portion including an annular tapered area that tapers in thickness between an upper boundary and a lower boundary and encloses an elevated area bounded by the upper boundary. The upper and/or lower boundary defines a shape having two lobes, each with an outer edge with a convex profile, and a connecting portion extending between the lobes, such that the connecting portion is defined by two outer edges extending between the outer edges of the lobes, wherein at least one of the outer edges of the connecting portion has a concave outer profile.Type: GrantFiled: September 26, 2014Date of Patent: June 19, 2018Assignee: Karsten Manufacturing CorporationInventors: Robert M. Boyd, Jeremy N. Snyder, Hiroshi Kawaguchi, James S. Thomas, Raymond J. Sander, Rick S. Wahlin, Akira Shimozuma
-
Patent number: 9987533Abstract: Golf clubs and golf club heads having a weight member that is configurable in multiple positions to alter the performance characteristics of the golf club head are presented. In some examples, the weight member may be arranged in a sole of the golf club head and may include ends having different weighting characteristics. For instance, one end may be heavier or denser than another end of the weight member. The difference in weight characteristics may be due to different materials used to form the different ends, different construction of the ends, and the like. The position of the weight member may be adjusted to alter the performance characteristics of the golf club head. For instance, the weight member may be removed and rotated to position a heavier end where a lighter end was previously positioned.Type: GrantFiled: February 10, 2016Date of Patent: June 5, 2018Assignee: Karsten Manufacturing CorporationInventors: Andrew G. V. Oldknow, James S. Thomas, Hiroshi Kawaguchi, Robert Boyd
-
Publication number: 20180151377Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.Type: ApplicationFiled: January 29, 2018Publication date: May 31, 2018Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
-
Patent number: 9984884Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.Type: GrantFiled: December 20, 2016Date of Patent: May 29, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
-
Publication number: 20180085644Abstract: A golf club head made out of multi-material is disclosed herein. More specifically, the golf club head in accordance with the present invention has at least a portion of the body of the golf club head that is further comprised out of a base layer and a lightweight cover layer. The base layer may have a plurality of cutouts to help reduce unnecessary mass and the lightweight cover layer may be made out of an ultra-lightweight material to further reduce the unnecessary mass.Type: ApplicationFiled: September 29, 2017Publication date: March 29, 2018Applicant: Acushnet CompanyInventor: Hiroshi Kawaguchi
-
Publication number: 20180061983Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: ApplicationFiled: October 20, 2017Publication date: March 1, 2018Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Yasuhiro OKAMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI
-
Publication number: 20180026099Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.Type: ApplicationFiled: May 25, 2017Publication date: January 25, 2018Applicant: Renesas Electronics CorporationInventors: Hironobu MIYAMOTO, Tatsuo NAKAYAMA, Atsushi TSUBOI, Yasuhiro OKAMOTO, Hiroshi KAWAGUCHI
-
Nitride semiconductor device using insulating films having different bandgaps to enhance performance
Patent number: 9853108Abstract: The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased.Type: GrantFiled: December 30, 2016Date of Patent: December 26, 2017Assignee: Renesas Electronics CorporationInventor: Hiroshi Kawaguchi -
Patent number: 9831339Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: GrantFiled: June 26, 2017Date of Patent: November 28, 2017Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi
-
Patent number: 9830990Abstract: Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.Type: GrantFiled: June 7, 2017Date of Patent: November 28, 2017Assignee: Rohm Co., Ltd.Inventors: Shintaro Izumi, Tomoki Nakagawa, Hiroshi Kawaguchi, Masahiko Yoshimoto
-
Publication number: 20170294538Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Yasuhiro OKAMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI
-
Publication number: 20170288046Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (?1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.Type: ApplicationFiled: March 20, 2017Publication date: October 5, 2017Applicant: Renesas Electronics CorporationInventors: Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Hiroshi KAWAGUCHI, Tatsuo NAKAYAMA
-
Publication number: 20170278558Abstract: Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.Type: ApplicationFiled: June 7, 2017Publication date: September 28, 2017Inventors: Shintaro IZUMI, Tomoki NAKAGAWA, Hiroshi KAWAGUCHI, Masahiko Yoshimoto
-
Patent number: 9724573Abstract: A golf club head enables the initial velocity of a ball to be increased and enables the carry to be lengthened. In some example structures, the golf club includes a face plate formed from metal and club head body (e.g., a crown and sole) formed from fiber reinforced plastic. A weighted body is provided inside the rearmost portion of the golf club head and a low rigidity portion whose width becomes gradually narrower as it approaches the rearmost portion is provided in the crown extending from the vicinity of the face plate to the rearmost portion.Type: GrantFiled: January 17, 2014Date of Patent: August 8, 2017Assignee: Karsten Manufacturing CorporationInventors: Hiroshi Kawaguchi, Michael L. Kelly, Hitoshi Kodama, Tsuneo Takano
-
Patent number: 9722062Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: GrantFiled: August 27, 2015Date of Patent: August 1, 2017Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi