Patents by Inventor Hiroshi Kawakubo
Hiroshi Kawakubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9401284Abstract: A semiconductor device includes: a substrate comprised by gallium arsenide; an active layer provided on the substrate; a first nickel-plated layer provided on a lower face of the substrate facing the active layer; a copper-plated layer provided on a lower face of the first nickel-plated layer; and a second nickel-plated layer provided on a lower face of the copper-plated layer.Type: GrantFiled: June 5, 2015Date of Patent: July 26, 2016Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Hiroshi Kawakubo
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Patent number: 9368405Abstract: A method for manufacturing a semiconductor device that includes steps of: (1) adhering a support substrate to a first surface of a wafer using an adhesive, the wafer including first and second scribe lines extending along first and second directions, respectively, (2) thinning the wafer, (3) forming a groove in a first scribe line excluding a region located in an outer peripheral portion of the wafer, the groove piercing the wafer from the first surface to a second surface opposite to the first surface to expose the adhesive, the first scribe line and the second scribe line demarcating chip regions; and (4) removing the adhesive by immersing the wafer adhered to the support substrate in a solvent such that the solvent permeates into the groove.Type: GrantFiled: January 29, 2015Date of Patent: June 14, 2016Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Toshiyuki Kosaka, Hiroshi Kawakubo
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Publication number: 20150270137Abstract: A semiconductor device includes: a substrate comprised by gallium arsenide; an active layer provided on the substrate; a first nickel-plated layer provided on a lower face of the substrate facing the active layer; a copper-plated layer provided on a lower face of the first nickel-plated layer; and a second nickel-plated layer provided on a lower face of the copper-plated layer.Type: ApplicationFiled: June 5, 2015Publication date: September 24, 2015Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Hiroshi Kawakubo
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Publication number: 20150221554Abstract: A method for manufacturing a semiconductor device that includes steps of: (1) adhering a support substrate to a first surface of a wafer using an adhesive, the wafer including first and second scribe lines extending along first and second directions, respectively, (2) thinning the wafer, (3) forming a groove in a first scribe line excluding a region located in an outer peripheral portion of the wafer, the groove piercing the wafer from the first surface to a second surface opposite to the first surface to expose the adhesive, the first scribe line and the second scribe line demarcating chip regions; and (4) removing the adhesive by immersing the wafer adhered to the support substrate in a solvent such that the solvent permeates into the groove.Type: ApplicationFiled: January 29, 2015Publication date: August 6, 2015Inventors: Toshiyuki KOSAKA, Hiroshi KAWAKUBO
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Patent number: 9082742Abstract: A semiconductor device includes: a substrate comprised by gallium arsenide; an active layer provided on the substrate; a first nickel-plated layer provided on a lower face of the substrate facing the active layer; a copper-plated layer provided on a lower face of the first nickel-plated layer; and a second nickel-plated layer provided on a lower face of the copper-plated layer.Type: GrantFiled: November 5, 2012Date of Patent: July 14, 2015Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Hiroshi Kawakubo
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Patent number: 8541298Abstract: A method for fabricating a semiconductor device having a GaN-based semiconductor layer on a first surface of a substrate made of SiC, a pad being provided on the GaN-based layer, includes: forming a first via hole in the substrate by etching, with fluorine based gas, from a second surface of the substrate opposite to the first surface, the etching being carried out with the GaN-based layer being used as an etch stopper; and forming a second via hole in the GaN-based semiconductor layer, with chlorine based gas, from a bottom surface of the first via hole, the etching being carried out with the pad being used as an etching stopper, the chlorine based gas being an etchant different from the fluorine based gas.Type: GrantFiled: July 18, 2011Date of Patent: September 24, 2013Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Hiroshi Kawakubo
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Publication number: 20120021598Abstract: A method for fabricating a semiconductor device having a GaN-based semiconductor layer on a first surface of a substrate made of SiC, a pad being provided on the GaN-based layer, includes: forming a first via hole in the substrate by etching, with fluorine based gas, from a second surface of the substrate opposite to the first surface, the etching being carried out with the GaN-based layer being used as an etch stopper; and forming a second via hole in the GaN-based semiconductor layer, with chlorine based gas, from a bottom surface of the first via hole, the etching being carried out with the pad being used as an etching stopper, the chlorine based gas being an etchant different from the fluorine based gas.Type: ApplicationFiled: July 18, 2011Publication date: January 26, 2012Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Hiroshi Kawakubo
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Patent number: 7332800Abstract: For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.Type: GrantFiled: June 4, 2004Date of Patent: February 19, 2008Assignee: Renesas Technology Corp.Inventors: Takashi Kikuchi, Ryosuke Kimoto, Hiroshi Kawakubo, Takashi Miwa, Chikako Imura, Takafumi Nishita, Hiroshi Koyama, Masanori Shibamoto, Masaru Kawakami
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Patent number: 7211892Abstract: In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 ?m or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3×10?3 (Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.Type: GrantFiled: June 7, 2005Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventors: Shiro Yamashita, Yoichi Abe, Kenichi Yamamoto, Ryosuke Kimoto, Hiroshi Kawakubo
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Publication number: 20070013083Abstract: Improvement in the mountability of a semiconductor device is aimed at. By preparing a package substrate which has a plurality of lands of NSMD structure, and the taking-out wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in the location of 180° symmetry, and printing solder by a printing method to the lands after the package assembly, the variation in the height of the solder coat between lands can be reduced, and improvement in the mountability of LGA (semiconductor device) is aimed at.Type: ApplicationFiled: July 10, 2006Publication date: January 18, 2007Inventors: Takashi Kikuchi, Koichi Kanemoto, Michiaki Sugiyama, Hiroshi Kawakubo
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Publication number: 20060151877Abstract: In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 ?m or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3×10?3 (Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.Type: ApplicationFiled: June 7, 2005Publication date: July 13, 2006Inventors: Shiro Yamashita, Yoichi Abe, Kenichi Yamamoto, Ryosuke Kimoto, Hiroshi Kawakubo
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Publication number: 20050040509Abstract: For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.Type: ApplicationFiled: June 4, 2004Publication date: February 24, 2005Inventors: Takashi Kikuchi, Ryosuke Kimoto, Hiroshi Kawakubo, Takashi Miwa, Chikako Imura, Takafumi Nishita, Hiroshi Koyama, Masanori Shibamoto, Masaru Kawakami
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Patent number: 6476467Abstract: The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.Type: GrantFiled: June 1, 2001Date of Patent: November 5, 2002Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems Ltd.Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama
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Publication number: 20010042906Abstract: Improvement is affected in uniformizing the thickness of a tape carrier package having a semiconductor chip in which bonding pads are disposed in such a way that the bonding pads are arranged concentratedly on one side of the semiconductor chip.Type: ApplicationFiled: June 1, 2001Publication date: November 22, 2001Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama
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Patent number: 6278176Abstract: The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.Type: GrantFiled: April 7, 2000Date of Patent: August 21, 2001Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama
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Patent number: 6214639Abstract: A method of producing a semiconductor device including a step of forming separation grooves in scribing regions defined at boundary portions between a plurality of semiconductor-device forming portions formed on a top surface of a semiconductor substrate; a step of defining portions of the scribing regions in the semiconductor substrate as substrate connecting portions; and a step of cutting off the substrate connecting portions along the separation grooves, to thereby separate the plurality of semiconductor-device forming portions into chips. These production steps contribute to a higher working efficiency in a later assembling process and to improved mass-production.Type: GrantFiled: August 3, 1999Date of Patent: April 10, 2001Assignee: Fujitsu LimitedInventors: Masaomi Emori, Mitsuji Nunokawa, Kenichi Hiratsuka, Masanori Ishii, Hiroshi Kawakubo
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Patent number: 6060770Abstract: The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.Type: GrantFiled: January 14, 1998Date of Patent: May 9, 2000Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama