Patents by Inventor Hiroshi Kawashima

Hiroshi Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6870979
    Abstract: An optical circuit device includes: a substrate and an optical waveguide layer having a core and a cladding formed on the substrate; an optical waveguide circuit of the core having an optical splitter for splitting light, an optical coupler for coupling light, a first connecting optical waveguide and a second connecting optical waveguide for connecting the optical splitter and the optical coupler, and the first and second connecting optical waveguides respectively having first and second phase adjustment means capable of varying the phases of a propagating light, the optical circuit device being formed such that the rate of change of the polarization difference of phases in the first phase adjustment means and the rate of change of the polarization difference of phases in the second phase adjustment means are different from each other with respect to the phase adjustment amounts when the first and second phase adjustment means perform phase adjustment.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: March 22, 2005
    Assignee: The Furukawa Electric Co., Ltd
    Inventors: Hiroshi Kawashima, Kazutaka Nara
  • Patent number: 6841459
    Abstract: A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: January 11, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Kawashima, Motoshige Igarashi, Keiichi Higashitani
  • Publication number: 20040266874
    Abstract: The object of the present invention is to provide a composition that has preventive or ameliorative action on symptoms or diseases caused by decreased brain function. This composition contains, as its active ingredient, arachidonic acid and/or a compound having arachidonic acid as a constituent fatty acid and, particularly, an alcohol ester of arachidonic acid or a triglyceride, phospholipid or glycolipid in which all or a portion of the constituent fatty acids are arachidonic acid.
    Type: Application
    Filed: August 10, 2004
    Publication date: December 30, 2004
    Inventors: Kengo Akimoto, Hiroshi Kawashima, Yoshiko Ono, Hiroshige Okaichi, Youko Okaichi
  • Publication number: 20040264836
    Abstract: An optical circuit device includes: a substrate and an optical waveguide layer having a core and a cladding formed on the substrate; an optical waveguide circuit of the core having an optical splitter for splitting light, an optical coupler for coupling light, a first connecting optical waveguide and a second connecting optical waveguide for connecting the optical splitter and the optical coupler, and the first and second connecting optical waveguides respectively having first and second phase adjustment means capable of varying the phases of a propagating light, the optical circuit device being formed such that the rate of change of the polarization difference of phases in the first phase adjustment means and the rate of change of the polarization difference of phases in the second phase adjustment means are different from each other with respect to the phase adjustment amounts when the first and second phase adjustment means perform phase adjustment.
    Type: Application
    Filed: October 7, 2003
    Publication date: December 30, 2004
    Applicant: The Furukawa Electric Co., Ltd.
    Inventors: Hiroshi Kawashima, Kazutaka Nara
  • Patent number: 6812020
    Abstract: The present invention discloses a process for producing lipid containing omega-9 highly unsaturated fatty acid by culturing in a medium a mutant strain obtained by mutation on a microorganism having the ability to produce arachidonic acid belonging to the genus Mortierella and so forth, in which &Dgr;12 desaturation activity is decreased or lost, but at least one of &Dgr;5 desaturation activity, &Dgr;6 desaturation activity and chain length elongation activity is elevated. Moreover, the present invention also discloses a process for producing omega-9 highly unsaturated fatty acid by collecting omega-9 highly unsaturated fatty acid from the culture or lipid described above.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: November 2, 2004
    Assignee: Suntory Limited
    Inventors: Kengo Akimoto, Hiroshi Kawashima, Sakayu Shimizu
  • Publication number: 20040208093
    Abstract: A disk recorder/player (1) including a skew adjusting means of a thin design is provided which includes a base (101), a disk rotation driving mechanism (102) for an optical disk (4), an optical pickup (103), first and second guide shafts (105, 106) to support the optical pickup (103) at opposite ends of the latter, an optical pickup moving means (104) guided by the first and second guide shafts (105, 106) in moving the optical pickup (103) radially of the optical disk (4), an elastic member (126) put in contact with the first and second guide shafts (105, 106) to force the first and second guide shafts (105, 106) in a direction generally perpendicular to the main side of the optical disk (4), an adjusting screw (127) put into contact with the first and second guide shafts (105, 106) from the opposite side of the elastic member (126) to move the first and second guide shafts (105, 106) in a direction opposite to the direction of forcing by the elastic member (126), and a skew adjusting means (109) which adjust
    Type: Application
    Filed: January 22, 2004
    Publication date: October 21, 2004
    Applicant: Sony Corporation
    Inventors: Kiyoshi Omori, Hidehiko Yamamoto, Masazumi Shiozawa, Hitoshi Taniguchi, Kazuya Sunami, Hiroshi Kawashima
  • Publication number: 20040180268
    Abstract: First, a correction is made for correcting the mask pattern configuration of a photomask (3) used for exposure in accordance with the space between a mask pattern and an adjacent mask pattern thereto and a desired configuration to be transferred from the mask pattern. Second, a correction is made for dividing the photomask (3) into a plurality of mesh regions (M) to correct the pattern configuration of the photomask (3) in accordance with the occupation rate (R) of the mask pattern in each of the mesh regions (M).
    Type: Application
    Filed: August 7, 2003
    Publication date: September 16, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Hiroshi Kawashima, Yoshitaka Yamada
  • Patent number: 6753246
    Abstract: The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: June 22, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Kawashima, Masakazu Okada, Takeshi Kitani, Motoshige Igarashi
  • Patent number: 6713480
    Abstract: Methods of using a compound, its pharmaceutically acceptable salts, and/or its pro-drug esters, in isolated form, to treat cancer, and methods for isolating, for formulating, and for administering the compound, salt, and/or pro-drug ester as an antitumor agent, wherein the compound, salt, or pro-drug ester has the following generic structure: wherein R1, R2, R3, R4, R5, R6, R7, R8, X1 and X2 are selected from specified residues, as described, and the dashed bond represents either a carbon-carbon single bond or a carbon-carbon double bond.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: March 30, 2004
    Assignee: Nereus Pharmaceuticals Inc.
    Inventors: Kenji Fukumoto, Shinkichi Kohno, Kaneo Kanoh, Tohru Asari, Hiroshi Kawashima, Hirokatsu Sekiya, Kazunori Ohmizo, Takeo Harada
  • Publication number: 20030216015
    Abstract: A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.
    Type: Application
    Filed: November 6, 2002
    Publication date: November 20, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hiroshi Kawashima, Motoshige Igarashi, Keiichi Higashitani
  • Patent number: 6631235
    Abstract: The present invention provides a planar lightwave circuit platform and its method for manufacturing by which the characteristics of the planar lightwave circuit become stable. In a planar lightwave circuit platform comprising quartz-based lower cladding layer (2), height adjusting layer (3), core layer (4), and upper cladding layer (5) formed in order on substrate (1), wherein the glass softening temperature of the height adjusting layer (3) is set to be higher than the glass softening temperatures and the temperatures for transparent-vitrification of the core layer (4) and upper cladding layer (5).
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: October 7, 2003
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Hiroshi Kawashima, Kazutaka Nara, Shiro Nakamura, Kazunori Watanabe
  • Publication number: 20030178647
    Abstract: The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.
    Type: Application
    Filed: April 22, 2003
    Publication date: September 25, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hiroshi Kawashima, Masakazu Okada, Takeshi Kitani, Motoshige Igarashi
  • Patent number: 6617218
    Abstract: A region around the gate of a PMOSFET that does not, at a minimum, affect the transistor characteristics is covered with a resist and a diagonal ion implantation for drain engineering is carried out in a P well region beneath gate electrode. Ions of a first conductive type are implanted in a portion wherein a well contact layer is formed so as to form well contact layer. The above described diagonal ion implantation and the ion implantation for forming the above described well contact layer are carried out so that when the depth is plotted along the longitudinal axis and the impurity concentration is plotted along the lateral axis in the impurity profile of well contact larger, impurity profile or the first conductive type that forms well contact layer covers profile of the impurities that form the impurity diffusion layer.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: September 9, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Kawashima
  • Patent number: 6602690
    Abstract: A process for the production of dihomo-&ggr;-linolenic acid comprising the steps of culturing a microorganism having an ability to produce araquidonic acid and having a reduced or lost &Dgr;5 desaturase activity to produce dihomo-&ggr;-linolenic acid or a lipid containing dihomo-&ggr;-linolenic acid, and recovering the dihomo-&ggr;-linolenic acid.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: August 5, 2003
    Assignee: Suntory, Ltd.
    Inventors: Hiroshi Kawashima, Kengo Akimoto, Hideaki Yamada, Sakayu Shimizu
  • Publication number: 20030112637
    Abstract: A method of designing a reflective surface of a reflector used in a vehicle lamp includes a first base curve generating step of generating a first base curve Q; a second base curve generating step of generating a plurality of second base curves R; and a surface shape generating step of generating a surface shape of the reflective surface RS, based on the first base curve and the plurality of second base curves, wherein the first base curve generating step includes repeating a step of generating one partial curve Qi and thereafter generating a subsequent partial curve Qi+1 so as to be connected to the partial curve, thereby generating one first base curve Q consisting of a plurality of partial curves Qi connected to each other, and wherein each partial curve Q1 is generated based on a shape parameter according thereto.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 19, 2003
    Applicant: KOITO MANUFACTURING CO., LTD.
    Inventors: Hiroshi Kawashima, Masashi Tatsukawa
  • Patent number: 6578996
    Abstract: A method of designing a reflective surface of a reflector used in a vehicle lamp includes a first base curve generating step of generating a first base curve Q; a second base curve generating step of generating a plurality of second base curves R; and a surface shape generating step of generating a surface shape of the reflective surface RS, based on the first base curve and the plurality of second base curves, wherein the first base curve generating step includes repeating a step of generating one partial curve Qi and thereafter generating a subsequent partial curve Qi+1 so as to be connected to the partial curve, thereby generating one first base curve Q consisting of a plurality of partial curves Qi connected to each other, and wherein each partial curve Qi is generated based on a shape parameter according thereto.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: June 17, 2003
    Assignee: Koito Manufacturing Co., Ltd.
    Inventors: Hiroshi Kawashima, Masashi Tatsukawa
  • Publication number: 20030100161
    Abstract: A region around the gate of a PMOSFET that does not, at a minimum, affect the transistor characteristics is covered with a resist and a diagonal ion implantation for drain engineering is carried out in a P well region beneath a gate electrode. Ions of a first conductive type are implanted in a portion wherein a well contact layer is formed so as to form well contact layer. The above described diagonal ion implantation and the ion implantation for forming the above described well contact layer are carried out so that when the depth is plotted along the longitudinal axis and the impurity concentration is plotted along the lateral axis in the impurity profile of well contact larger, impurity profile or the first conductive type that forms well contact layer covers profile of the impurities that form the impurity diffusion layer.
    Type: Application
    Filed: July 11, 2002
    Publication date: May 29, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Kawashima
  • Patent number: 6565250
    Abstract: A designing method of a reflective surface RS according to the present invention has a step of generating an XY curve Q on an XY plane including the X-axis (optical axis) and Y-axis; a step of, at each of a plurality of base points P existing on the XY curve Q, generating an XZ curve R on a plane (UZ plane) including the base point P and being parallel to a reflection direction of light at the base point P and normal to the XY plane; and a step of generating a surface shape of the reflective surface RS, based on the XY curve Q and the plurality of XZ curves R. This substantiates a method of designing a reflective surface of a reflector in a vehicle lamp with improved controllability of a light distribution pattern and with improved efficiency of a designing work.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: May 20, 2003
    Assignee: Koito Manufacturing Co., Ltd.
    Inventors: Hiroshi Kawashima, Masashi Tatsukawa
  • Patent number: 6563148
    Abstract: The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: May 13, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Kawashima, Masakazu Okada, Takeshi Kitani, Motoshige Igarashi
  • Patent number: 6561687
    Abstract: The shape of a horizontal cross section Sho including a reference axis Ax on a reflective surface 14a is set to a curved shape for focusing and reflecting light from a light source 12a closer to the reference axis Ax within the horizontal cross section Sho. The shape of a vertical cross section including the axis in the direction of emitting reflected light at each of the points on the horizontal cross section including the reference axis Ax on the reflective surface 14a is set to a curved shape for reflecting the light from the light source in substantially parallel to the axis in the direction of emitting the reflected light in a central reflective area near the lateral reference axis Ax. The shapes of peripheral reflective areas 14a2 on both sides of the central reflective area are respectively set to curved shapes for focusing and reflecting the light from the light source 12a closer to the axis in the direction of emitting the reflected light.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: May 13, 2003
    Assignee: Koito Manufacturing Co., Ltd.
    Inventors: Hideaki Satsukawa, Yasuyuki Amano, Hiroshi Kawashima