Patents by Inventor Hiroshi Kimura

Hiroshi Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190158322
    Abstract: To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 23, 2019
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Hiroshi KIMURA, Haoqiong CHEN, Yehui SUN
  • Patent number: 10298890
    Abstract: A vehicle display device includes a projector which emits display light of an image indicating vehicle information, a controller that controls luminance of the display light, and a screen that displays the image when the display light is projected to the screen. The screen has a convex portion that protrudes to a near side in a direction in which the image is visually recognized, and a concave portion that is recessed to a far side. In addition, the controller controls the luminance of the display light so that the display light projected to the convex portion (first parts) has higher luminance than that of the display light projected to the concave portion (second parts).
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: May 21, 2019
    Assignee: DENSO CORPORATION
    Inventors: Kenichiro Karikomi, Keiichi Iwashima, Yoshihisa Hasegawa, Hiroshi Kimura
  • Patent number: 10240661
    Abstract: An end fixing structure of a composite wire rod includes a composite wire rod, a wedge body that is formed into a cylindrical shape with an enlarging diameter from a front end portion, wherein an inner wall surface is formed for engaging with the outer surface of the composite wire rod which is copied onto the inner wall surface, and a sleeve provided on an outer peripheral side of the wedge body and having a conical and hollow inner structure, and the wedge body consists of a plurality of divided wedge bodies, facing each other on their divided surfaces with a space therebetween, and the inner wall surface in the divided wedge body is made of microscopic irregularities, thereby shortening a processing time and maintaining a sufficient gripping power over long term.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: March 26, 2019
    Assignee: TOKYO ROPE MFG. CO., LTD.
    Inventors: Daisuke Manabe, Shunji Hachisuka, Hiroshi Kimura, Fumihiro Matsuda, Nobuhiro Kai, Hiroyuki Shimmura, Kohsuke Ashizuka
  • Publication number: 20190048414
    Abstract: A method for determining a nucleic acid sequence of a target gene expressed in a subject cell, the method including: comprehensively determining mRNA nucleic acid sequences in the subject cell, and identifying a nucleic acid sequence having a nucleic acid sequence of a portion of the target gene, from among the determined mRNA nucleic acid sequences, in which the identified nucleic acid sequence is a nucleic acid sequence of the target gene.
    Type: Application
    Filed: March 2, 2017
    Publication date: February 14, 2019
    Inventors: Yasuyuki OHKAWA, Kazumitsu MAEHARA, Hiroshi KIMURA, Yuko SATO
  • Patent number: 10193714
    Abstract: To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 29, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Hiroshi Kimura, Haoqiong Chen, Yehui Sun
  • Patent number: 10074740
    Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: September 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
  • Publication number: 20180234270
    Abstract: To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 16, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Hiroshi KIMURA, Haoqiong Chen, Yehui Sun
  • Patent number: 9996099
    Abstract: Disclosed herein is a bias generator circuit for generating a desired bias voltage or bias current using a simple configuration. The bias generator circuit includes a voltage generator circuit, a comparator, and a clock gating circuit. The voltage generator circuit increases or decreases its output voltage in accordance with the number of clock cycles of a given clock signal. The comparator compares the output voltage of the voltage generator circuit to a reference voltage. The clock gating circuit receives, as a control signal, output of the comparator and determines, in accordance with the control signal, whether or not to pass the clock signal to the voltage generator circuit. Thus, the output voltage of the voltage generator circuit, i.e., a bias voltage, is set to be close to the reference voltage.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 12, 2018
    Assignee: Socionext, Inc.
    Inventor: Hiroshi Kimura
  • Patent number: 9969041
    Abstract: A deformable thin object spreading device and method are disclosed. The device includes a control part configured to: control a clamping unit and a moving mechanism to cause the clamping unit to clamp a first point of a deformable thin object; cause an endpoint detecting part to detect a first endpoint; control the clamping unit and the moving mechanism to cause the clamping unit to clamp the first endpoint; cause the endpoint detecting part to detect a second endpoint; control the clamping unit and the moving mechanism to cause the clamping unit to clamp both of the first endpoint and the second endpoint; cause the endpoint detecting part to detect a third endpoint; and control the clamping unit and the moving mechanism to cause the clamping unit to clamp both of the first endpoint or the second endpoint and the third endpoint of the deformable thin object.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: May 15, 2018
    Assignees: Seven Dreamers Laboratories, Inc., Panasonic Corporation
    Inventors: Yoshimasa Endo, Hiroshi Kitagawa, Hiroshi Kimura
  • Patent number: 9914900
    Abstract: This liquid detergent contains an ?-sulfofatty acid ester salt (component (a)), an alkylbenzene sulfonate (component (b)), a polyoxyethylene alkyl ether sulfate (component (c)), and an alkanolamine (component (d)). The amount of the component (a) is 5% by mass or greater; the total amount of the component (b) and the component (c) is 5% by mass or greater; the total amount of the component (a), the component (b), and the component (c) is 10% by mass to 50% by mass, the mass ratio represented by (d)/(a) is 1/5 or greater, and the mass ratio represented by (a)/((b)+(c)) is 1 or less.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 13, 2018
    Assignee: Lion Corporation
    Inventors: Atsunori Morigaki, Hiroshi Kimura, Hiroshi Konta
  • Patent number: 9847758
    Abstract: A low noise amplifier includes: first and seventh transistors configured to respectively receive first and second input signals; second, third, and fifth transistors connected to the first transistor; eighth, ninth, and eleventh transistors connected to the seventh transistor; a third resistive element; fourth and tenth transistors respectively connected to the third and ninth transistors; sixth and twelfth transistors respectively connected to second and first output terminals; and first and second resistive elements.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: December 19, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Takahiro Bokui, Hiroshi Kimura
  • Publication number: 20170349789
    Abstract: It has conventionally been difficult to achieve a sheet adhesive which adheres in a low temperature (from 20 to 90° C.), and has both of softness and high adhering strength. The present invention realizes a sheet adhesive capable of adhering in a low temperature (from 20 to 90° C.) which exhibits a high adhesiveness in spite of being a soft sheet of thin film, by forming a simulated multiple layer by using an elastomer as a substrate layer, and by forming a reactive layer by means of spraying or application. A sheet adhesive including a substrate layer and a reactive layer, wherein the substrate layer includes a component (A) and a component (B) below, and the reactive layer is formed with a liquid agent including a component (C) below in an amount of from 0.014 by mass to 45% by mass, component (A): a urethane elastomer, component (B): an epoxy resin, component (C): an amine compound and/or phenol compound.
    Type: Application
    Filed: May 24, 2017
    Publication date: December 7, 2017
    Inventors: Hiroshi KIMURA, Yoshihide ARAI
  • Patent number: D809907
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: February 13, 2018
    Assignee: TOKYO ROPE MFG. CO., LTD.
    Inventors: Daisuke Manabe, Shunji Hachisuka, Hiroshi Kimura, Yoshihiro Tamura
  • Patent number: D814279
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: April 3, 2018
    Assignee: TOKYO ROPE MFG. CO., LTD.
    Inventors: Daisuke Manabe, Shunji Hachisuka, Hiroshi Kimura, Fumihiro Matsuda, Kohsuke Ashiduka
  • Patent number: RE46773
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 3, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
  • Patent number: D815940
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: April 24, 2018
    Assignee: TOKYO ROPE MFG. CO., LTD.
    Inventors: Daisuke Manabe, Shunji Hachisuka, Hiroshi Kimura, Fumihiro Matsuda, Kohsuke Ashiduka
  • Patent number: D821857
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 3, 2018
    Assignee: TOKYO ROPE MFG. CO., LTD.
    Inventors: Daisuke Manabe, Shunji Hachisuka, Hiroshi Kimura, Fumihiro Matsuda, Kohsuke Ashiduka
  • Patent number: D823676
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 24, 2018
    Assignee: TOKYO ROPE MFG. CO., LTD.
    Inventors: Daisuke Manabe, Shunji Hachisuka, Hiroshi Kimura, Yoshihiro Tamura
  • Patent number: D825320
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: August 14, 2018
    Assignee: TOKYO ROPE MFG. CO., LTD.
    Inventors: Daisuke Manabe, Shunji Hachisuka, Hiroshi Kimura, Fumihiro Matsuda, Kohsuke Ashiduka
  • Patent number: D826037
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 21, 2018
    Assignee: TOKYO ROPE MFG. CO., LTD.
    Inventors: Daisuke Manabe, Shunji Hachisuka, Hiroshi Kimura, Yoshihiro Tamura