Abstract: In a semiconductor memory device for performing a memory operation by controlling an internal voltage and a memory operation voltage, a cycle of an internal clock signal is varied in accordance with operation time characteristics of the memory operation.

Abstract: In a semiconductor memory device for performing a memory operation by controlling an internal voltage and a memory operation voltage, a cycle of an internal clock signal is varied in accordance with operation time characteristics of the memory operation.

Abstract: A semiconductor memory device includes: a plurality of sectioned memory arrays; a comparing circuit; and a predetermined terminal, and configured so that the test mode, the same test data is written in simultaneously into a plurality of memory arrays, and when the written data is read out, the data is read out simultaneously from a plurality of memory arrays so that the comparing circuit compares the simultaneously read-out data outputs, if the result of the comparison shows agreement, the data itself is outputted through the predetermined terminal, while if the result of the comparison shows disagreement, the predetermined terminal is set into a high-impedance state, or the predetermined terminal is made to output a particular voltage other than the voltages representing the `1` level and the `0` level.