Patents by Inventor Hiroshi Koguma

Hiroshi Koguma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND MOBILE TELEPHONE
    Publication number: 20150214076
    Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.
    Type: Application
    Filed: April 9, 2015
    Publication date: July 30, 2015
    Inventors: Takashi KITAHARA, Hiroshi KOGUMA
  • Semiconductor device with peeling prevention marks and shield film
    Patent number: 9030032
    Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Kitahara, Hiroshi Koguma
  • SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND MOBILE TELEPHONE
    Publication number: 20120295668
    Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 22, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi KITAHARA, Hiroshi KOGUMA
  • Semi-conductor device
    Patent number: 5018004
    Abstract: A semiconductor chip package technology which uses thin film wiring from the chip to the package terminals for increased line density and decreased parasitic capacitance and uses a thin film adhesion layer for improved heat conductivity between the package substrate and its sealing cap. The package uses a thin conductor film deposited along the element mounting surface of a sintered substrate. An adhesion layer, to provide a high quality bond between the sealing cap and substrate, is then deposited on the substrate peripheral area by successively laminating metal and metallized layers, or by depositing a single layer of low metal glass. The adhesion layer is thinner and of larger area than thick film technology, for improved heat conduction.
    Type: Grant
    Filed: November 28, 1989
    Date of Patent: May 21, 1991
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takayuki Okinaga, Shouji Matsugami, Yuuji Shirai, Kanji Otsuka, Hiroshi Koguma, Takashi Emata