Patents by Inventor Hiroshi Komatsu

Hiroshi Komatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060250530
    Abstract: Instinctive operation of editing parameters of waveform is provided. Tabs 38, 40 and 42 are displayed on a display screen 14 to show existence of parameter edit screen layers of different combinations of characters, waveforms and channels. If one of the tabs are selected the display is switched to show the corresponding parameter edit screen layer. Channel characters or waveforms are displayed on the tabs 38, 40 and 42 and are changed dynamically according to the setting so that a user can easily realize setting outlines of the respective channels at a glance.
    Type: Application
    Filed: April 20, 2006
    Publication date: November 9, 2006
    Inventors: Toshio Sugiyama, Susan Adam, Hiroshi Komatsu, Kazumasa Ito, Takayuki Hayase, Toru Takai
  • Patent number: 7063744
    Abstract: There is provided a coating device which can quickly cope with a change in size of a container. A pair of coating belts (annular belts) (11, 15) are arranged on two sides of a conveyor (10). The coating belt (15) is rotated at a high speed while the coating belt (11) is rotated at a low speed. A container (bottle) (1) on the conveyor (10) is coated while being rotated. When the size of the container (1) is to be changed, a pressing roller (57) is moved by an adjusting mechanism (50) in accordance with the size of the container (1).
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: June 20, 2006
    Assignee: Asahi Breweries Ltd.
    Inventors: Hiroshi Komatsu, Gen Okano
  • Patent number: 7042543
    Abstract: A liquid crystal display including: a first transparent substrate coated with a first alignment layer, a second transparent substrate coated with a second alignment layer, the second substrate facing the first transparent substrate, a liquid crystal layer between the substrates, a polarizer attached on the outer surfaces of the substrates, a pair of electrodes formed on the first substrates, and a driving circuit applying signal voltage to the electrodes. The liquid crystal molecules adjacent to the first substrate is rotated by applying the voltage, but, the liquid crystal molecule adjacent to the second substrate is fixed regardless of the applied voltage. The electrode pair, substantially straight data and common electrodes, are inclined at an angle with respect to a gate line.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: May 9, 2006
    Assignee: LG Philips LCD Co., Ltd
    Inventor: Hiroshi Komatsu
  • Publication number: 20060054083
    Abstract: There is provided a coating device which can quickly cope with a change in size of a container. A pair of coating belts (annular belts) (11, 15) are arranged on two sides of a conveyor (10). The coating belt (15) is rotated at a high speed while the coating belt (11) is rotated at a low speed. A container (bottle) (1) on the conveyor (10) is coated while being rotated. When the size of the container (1) is to be changed, a pressing roller (57) is moved by an adjusting mechanism (50) in accordance with the size of the container (1).
    Type: Application
    Filed: August 18, 2005
    Publication date: March 16, 2006
    Inventors: Hiroshi Komatsu, Gen Okano
  • Patent number: 6960420
    Abstract: A photosensitive resin composition is disclosed that includes (A) a heat-resistant polymer of the general formula (1): (where the symbols are as defined in the specification), (B) a photoreactive compound, and (C) a solvent. A relief pattern is formed from the composition by applying the composition to a support substrate and drying it to form a photosensitive resin film; exposing the dried film; developing the exposed film using an alkaline aqueous solution; and heating the developed photosensitive resin film. Also disclosed is an electronic component that includes an electronic device having such a pattern.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: November 1, 2005
    Assignees: Hitachi Chemical Dupont Microsystems LTD, Hitachi Chemical Dupont Microsystem L.L.C.
    Inventor: Hiroshi Komatsu
  • Publication number: 20040207793
    Abstract: A liquid crystal display including: a first transparent substrate coated with a first alignment layer, a second transparent substrate coated with a second alignment layer, the second substrate facing the first transparent substrate, a liquid crystal layer between the substrates, a polarizer attached on the outer surfaces of the substrates, a pair of electrodes formed on the first substrates, and a driving circuit applying signal voltage to the electrodes. The liquid crystal molecules adjacent to the first substrate is rotated by applying the voltage, but, the liquid crystal molecule adjacent to the second substrate is fixed regardless of the applied voltage. The electrode pair, substantially straight data and common electrodes, are inclined at an angle with respect to a gate line.
    Type: Application
    Filed: May 12, 2004
    Publication date: October 21, 2004
    Inventor: Hiroshi Komatsu
  • Patent number: 6804876
    Abstract: A method of producing a chip inductor including the steps of inserting a conductive wire made of a metallic wire into a metallic mold, supporting both end portions of the conductive wire on support portions provided on inner surfaces of the metallic mold so as to position the conductive wire in the approximate center portion of the metallic mold, casting magnetic ceramic slurry into the metallic mold, molding the ceramic slurry case in the metallic mold by wet pressing to obtain a molding body having the conductive wire embedded therein, firing the molding body, and forming external electrodes on both end surfaces of the fired magnetic core such that the external electrodes are connected to both end portions of the conductive wire.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: October 19, 2004
    Assignee: Murata Manufacturing Co., LTD
    Inventors: Yoichiro Ito, Takahiro Yamamoto, Hiroshi Komatsu, Tadashi Morimoto
  • Patent number: 6803982
    Abstract: An in-plane switching mode liquid crystal display device is disclosed which comprises first and second substrates, a plurality of gate and data bus lines formed on said first substrate to define a plurality of pixel regions, a common bus line aligned in each pixel regions of the first substrate, a thin film transistor (TFT) formed at each pixel regions of the first substrate, a data electrode which is formed on a gate insulator of the TFT and has a portion overlapping the common bus line for forming a first storage capacitor, a passivation layer formed over the data electrode and the TFT, a common electrode which is formed on the passivation layer so as to overlap the gate and data bus lines and has a portion overlapping said data electrode for forming a second storage capacitor, and a liquid crystal layer formed between the first and second substrates.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: October 12, 2004
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Hiroshi Komatsu
  • Publication number: 20040197970
    Abstract: In a complete depletion type SOI transistor, the roll-off of a threshold value is suppressed, independently from the formation of an SOI film to be thinner. As for a semiconductor device (1), the impurity concentration in a channel formation portion (10) is implanted not uniformly along the length direction of a gate (2) in the complete depletion type silicon on insulation (SOI) transistor. In other words, high concentration regions (11) where impurity concentrations are higher than that at a central portion in the end parts of the channel formation portion (10) on the side of a source (4) and a drain (5).
    Type: Application
    Filed: April 26, 2004
    Publication date: October 7, 2004
    Inventor: Hiroshi Komatsu
  • Patent number: 6800237
    Abstract: A plurality of feedthrough holes are efficiently formed on the present invention by splitting a laser beam emitted from a laser source into plural laser beams by allowing the beam to pass through a diffraction grating, followed by simultaneously forming a plurality of the feedthrough holes on the ceramic green sheet by irradiating the ceramic green sheet with the split laser beam.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: October 5, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takahiro Yamamoto, Hiroshi Komatsu, Tadashi Morimoto, Takashi Shikama
  • Patent number: 6773970
    Abstract: A method of producing a semiconductor device able to prevent outward diffusion of an impurity from a gate electrode and improve the device quality, the method comprising the steps of forming a gate electrode made of a semiconductor layer on a substrate (preferably SOI substrate) via a gate insulating film, forming a first insulating film coating the gate electrode by ALD, forming a second insulating film on a first insulating film, introducing an impurity to a substrate (preferably silicon active layer of the SOI wafer) to form a source/drain region by self-alignment with respect to the gate electrode, and forming an interlayer insulating film on the second insulating film.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: August 10, 2004
    Assignee: SonyCorporation
    Inventor: Hiroshi Komatsu
  • Publication number: 20040142275
    Abstract: A photosensitive resin composition is disclosed that includes (A) a heat-resistant polymer of the general formula (1): 1
    Type: Application
    Filed: November 6, 2003
    Publication date: July 22, 2004
    Inventor: Hiroshi Komatsu
  • Patent number: 6741312
    Abstract: An in-plane switching mode liquid crystal display device comprises a substrate, a pixel region, a common bus line, a thin film transistor, a data electrode, a passivation layer over the data electrode and the thin film transistor, and a common electrode. The pixel region lies on the substrate. The common bus line is aligned in the pixel region. The thin film transistor is coupled to the pixel region and the pixel regions comprises a gate electrode and a gate insulator having a portion overlying the gate electrode. The data electrode lies over the gate insulator and has a portion overlying the common bus line to form a first storage capacitor. The passivation layer overlies the data electrode and the thin film transistor. The common electrode overlies the passivation layer and has a portion overlying the data electrode to form a second storage capacitor.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: May 25, 2004
    Assignee: LG Electronics Inc.
    Inventor: Hiroshi Komatsu
  • Patent number: 6718625
    Abstract: An method of manufacturing an inductor having a large current capacity which includes a magnetic sintered body formed via wet pressing treatment and a coil assembly disposed within the magnetic sintered body. The coil assembly is defined by a substantially cylindrical magnetic core member which is wound by a coil. Both ends of the coil of the coil assembly are respectively and electrically connected to an input electrode and an output electrode which are respectively disposed on two mutually facing end surfaces of the magnetic sintered body.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: April 13, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichiro Ito, Toshio Kawabata, Takahiro Yamamoto, Hiroshi Komatsu, Tadashi Morimoto, Takashi Shikama
  • Publication number: 20040014306
    Abstract: An MIS transistor that permits freely controlling in a continuous manner a work function in relation to a gate insulation film of a gate electrode to values that differ from a characteristic value of the material that constitutes the gate electrode and, as a result, permits continuously controlling a Vth. For MIS transistors (100A) and (100B), the gate electrode (10) has a multi layer structure of metal layers (11), (12), (13) of metals having distinct work functions and, moreover, the first metal layer (11) that is in contact with the gate insulation film (2) is formed at film thickness of 5 debye length of less, by atomic layer CVD.
    Type: Application
    Filed: July 28, 2003
    Publication date: January 22, 2004
    Inventor: Hiroshi Komatsu
  • Publication number: 20030201499
    Abstract: A gate oxide film is formed on a silicon substrate, and a gate electrode is formed on the oxide film. The gate electrode is a polysilicon film that is given p+ conductivity because of doping with B. An Si3N4 film is formed on the top surface of the gate electrode and sidewall spacers of Si3N4 are formed on the side walls of the gate electrode. An interlayer insulating film of SiO2 is formed on the Si3N4 film, the sidewall spacers, and a LOCOS oxide film. This structure inhibits diffusion of B from the gate electrode to the interlayer insulating film in a heating process that is executed after the formation of the gate electrode.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 30, 2003
    Inventor: Hiroshi Komatsu
  • Patent number: D482714
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: November 25, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroshi Komatsu
  • Patent number: D483050
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: December 2, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideki Kawai, Hiroshi Komatsu
  • Patent number: D487476
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: March 9, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroshi Komatsu
  • Patent number: D495353
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: August 31, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroshi Komatsu