Patents by Inventor Hiroshi Kondou

Hiroshi Kondou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11244026
    Abstract: A computer-implemented optimization problem arithmetic method includes, receiving a combinatorial optimization problem, selecting a first arithmetic circuit from among a plurality of arithmetic circuits based on a scale or a requested accuracy of the combinatorial optimization problem and a partition mode that defines logically divided states of each of the plurality of arithmetic circuits, and causing the first arithmetic circuit to execute an arithmetic operation of the combinatorial optimization problem.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 8, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroshi Yagi, Noriyuki Itakura, Noriaki Shimada
  • Patent number: 11106761
    Abstract: A computer-implemented optimization problem arithmetic method includes receiving a combinatorial optimization problem, determining, based on scale or a requested accuracy of the combinatorial optimization problem, a partition mode and an execution mode, the partition mode defining a logically divided state of an arithmetic circuit, the execution mode defining a range of hardware resources to be utilized in arithmetic operation for each of partitions generated by logically dividing the arithmetic circuit, and causing the arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem in accordance with the determined partition mode and the determined execution mode.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: August 31, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroyuki Izui, Tatsuhiro Makino, Noriaki Shimada
  • Patent number: 10628056
    Abstract: A permission setting register stores therein information indicating whether or not access is to be permitted to each node, per segment of a shared memory. When an abnormality occurs in a node, a permission canceling unit sets, for a segment that the abnormal node has been using, information in the permission setting register, the information corresponding to the abnormal node, to not permit access. When there is an access request from a remote node to a shared memory segment, a checking unit determines, with hardware, whether or not the access is permitted, based on the permission setting register, an access token included in the access request, and a memory token register.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: April 21, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Kondou
  • Publication number: 20200089729
    Abstract: A computer-implemented optimization problem arithmetic method includes determining, based on management information indicating a partition mode that defines a logically divided state of each of a plurality of arithmetic circuits and utilization information relating to each of the plurality of arithmetic circuits, a partition mode of each of the plurality of arithmetic circuits, receiving a combinatorial optimization problem, selecting, based on information relating to scale or requested accuracy of the combinatorial optimization problem and the determined partition mode of each of the plurality of arithmetic units, a first arithmetic circuit from among the plurality of arithmetic circuits, and causing the selected first arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem based on a first partition mode determined as the partition mode of the first arithmetic circuit.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroshi Yagi, Noriyuki Itakura, Noriaki Shimada
  • Publication number: 20200090051
    Abstract: An optimization problem operation method include accepting a combinatorial optimization problem to an operation unit that is capable of being divided into a plurality of partitions logically and solving the combinatorial optimization problem. The method include deciding a partition mode that prescribes a logical division state of the operation unit and an execution mode that prescribes a range of hardware resources used in an operation in the partition mode according to a scale or a requested precision of the combinatorial optimization problem. The method include causing execution of operations of the combinatorial optimization problem in parallel in the operation unit with the partition mode and the execution mode decided, based on the number of times obtained by dividing the number of times of execution of the combinatorial optimization problem by the number of divisions corresponding to the execution mode.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Noriaki Shimada, Hiroyuki Izui, Hiroshi Kondou, Tatsuhiro Makino
  • Publication number: 20200089728
    Abstract: A computer-implemented optimization problem arithmetic method includes, receiving a combinatorial optimization problem, selecting a first arithmetic circuit from among a plurality of arithmetic circuits based on a scale or a requested accuracy of the combinatorial optimization problem and a partition mode that defines logically divided states of each of the plurality of arithmetic circuits, and causing the first arithmetic circuit to execute an arithmetic operation of the combinatorial optimization problem.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroshi Yagi, Noriyuki Itakura, Noriaki Shimada
  • Publication number: 20200089475
    Abstract: A computer-implemented optimization problem arithmetic method includes receiving a combinatorial optimization problem, determining, based on scale or a requested accuracy of the combinatorial optimization problem, a partition mode and an execution mode, the partition mode defining a logically divided state of an arithmetic circuit, the execution mode defining a range of hardware resources to be utilized in arithmetic operation for each of partitions generated by logically dividing the arithmetic circuit, and causing the arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem in accordance with the determined partition mode and the determined execution mode.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroyuki Izui, Tatsuhiro Makino, Noriaki Shimada
  • Patent number: 10198365
    Abstract: An information processing system includes: a shared memory including a plurality of regions comprising first region and second region; a memory token storing unit configured to store memory tokens, each of the memory tokens controlling access to a region of the shared memory; an access token storing unit configured to store access tokens for accessing a specific region of the shared memory, the access tokens including first access token to access the first region and second access token to access the second region; a processor configured to add the access tokens to a request for accessing the first region and transmit the request including the added access tokens; and a determination circuit configured to receive the transmitted request including the added access tokens, compare the added access tokens with a memory token corresponding to the first region, and control access to the first region based on the comparison.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: February 5, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Kondou
  • Patent number: 10176035
    Abstract: A system for migrating a virtual machine includes: a first device; and a second device. The first device notifies the second device of failure information indicating that data transported to the second device includes an error originated from the first device, when the error is detected from a storage area in the first device. The second device writes a second identifier, whose value is different from that of a first identifier, into a memory of the second device while associating the second identifier with a second address, the second address being to serve as a copy destination of data indicated by the failure information, wherein the first identifier indicates that data in the second address includes an error originated from the second device, and the second identifier serves as an identifier indicating that data in the second address includes an error originated from the first device.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: January 8, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Hayato Koike, Hiroshi Kondou, Takafumi Anraku, Kenji Gotsubo
  • Publication number: 20170177254
    Abstract: A permission setting register stores therein information indicating whether or not access is to be permitted to each node, per segment of a shared memory. When an abnormality occurs in a node, a permission canceling unit sets, for a segment that the abnormal node has been using, information in the permission setting register, the information corresponding to the abnormal node, to not permit access. When there is an access request from a remote node to a shared memory segment, a checking unit determines, with hardware, whether or not the access is permitted, based on the permission setting register, an access token included in the access request, and a memory token register.
    Type: Application
    Filed: November 10, 2016
    Publication date: June 22, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Kondou
  • Publication number: 20170177508
    Abstract: A segment-information notifying unit in the home node notifies the number of the segment in the shared memory 43, which has been used by the faulty node, to each of the normal remote nodes, and it gives an instruction to temporarily stop the access on a per-segment basis. Then, a memory-access token setting unit sets a new token to the memory token register that corresponds to the shared memory segment that has been used by the faulty node, and it notifies the new token to each of the normal remote nodes. Then, an access resuming unit notifies each of the normal remote nodes of access resumption.
    Type: Application
    Filed: November 2, 2016
    Publication date: June 22, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Kondou
  • Publication number: 20170031745
    Abstract: A system for migrating a virtual machine includes: a first device; and a second device. The first device notifies the second device of failure information indicating that data transported to the second device includes an error originated from the first device, when the error is detected from a storage area in the first device. The second device writes a second identifier, whose value is different from that of a first identifier, into a memory of the second device while associating the second identifier with a second address, the second address being to serve as a copy destination of data indicated by the failure information, wherein the first identifier indicates that data in the second address includes an error originated from the second device, and the second identifier serves as an identifier indicating that data in the second address includes an error originated from the first device.
    Type: Application
    Filed: July 22, 2016
    Publication date: February 2, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hayato Koike, Hiroshi Kondou, Takafumi ANRAKU, Kenji GOTSUBO
  • Patent number: 9535492
    Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to: determine whether or not a difference between a total of power consumption values of physical or virtual computers and a preset upper-limit value satisfies a certain condition; select, in ascending order of priorities stored in a first storage and set based on details of processing executed by the computers, any of the computers as a target whose power consumption is to be reduced, when the difference satisfies the certain condition; and switch the computer selected to a state in which the power consumption is reduced.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: January 3, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Fumiaki Yamana, Hiroshi Kondou, Kenji Gotsubo
  • Publication number: 20160210248
    Abstract: An information processing system includes: a shared memory including a plurality of regions comprising first region and second region; a memory token storing unit configured to store memory tokens, each of the memory tokens controlling access to a region of the shared memory; an access token storing unit configured to store access tokens for accessing a specific region of the shared memory, the access tokens including first access token to access the first region and second access token to access the second region; a processor configured to add the access tokens to a request for accessing the first region and transmit the request including the added access tokens; and a determination circuit configured to receive the transmitted request including the added access tokens, compare the added access tokens with a memory token corresponding to the first region, and control access to the first region based on the comparison.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 21, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Kondou
  • Patent number: 9229820
    Abstract: An information processing device, including: a memory; a processing unit which operates a virtual machine, an operating system which is executed on the virtual machine, and a hypervisor which controls the virtual machine; and a control unit which controls a system including the memory and the processor. The processing unit stops the operating system when detecting an error of the hypervisor, notifies the control unit of a first memory area used by the hypervisor, stops the hypervisor, changes a memory area used by the hypervisor into a second memory area different from the first memory area notified by the control unit, starts the hypervisor using the second memory area as an available area, starts the operating system, and reads data in the first memory area, and writes the data to a file as a dump file of the hypervisor.
    Type: Grant
    Filed: May 26, 2013
    Date of Patent: January 5, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Kenji Okano
  • Publication number: 20150269092
    Abstract: An access blocking unit blocks an access to a failed segment by using tokens in hardware and a replacing unit performs a process for replacing the failed segment with a replacement segment. For each segment of a shared memory, an application recognizing unit recognizes the node numbers of nodes that are given access permission and PIDs of applications and records them in the management table. When a failure occurs in the shared memory, an access stopping unit identifies applications that use the failed segment including applications of different nodes by using the management table and informs the applications of stop of the use of the failed segment.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi KONDOU, Reiji WATANABE
  • Patent number: 9122597
    Abstract: Disclosed is an information processing device provided with: a plurality of processing units each having a TLB (Translation Lookaside Buffer); a means for acquiring a designation of a processing unit, from among the plurality of processing units, where TLB information is to be collected, and for acquiring a designation of the timing at which the TLB information is to be collected; and a means for collecting the TLB information from the designated processing unit at the designated timing.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 1, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Takafumi Anraku, Fumiaki Yamana, Hiroshi Kondou
  • Patent number: 9032482
    Abstract: An information processing apparatus is capable of performing a plurality of processes in parallel, and includes a plurality of operation components each including individual components, which are provided for respective processes to be performed in parallel. A control unit permits activation of as many operation components as the number of right-to-use licenses, out of the operation components. When detecting an abnormality in an individual component included in an active operation component, the control unit deactivates the other individual components of the operation component including the abnormal individual component, and activates another inactive operation component.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kondou, Takafumi Anraku
  • Patent number: 9015535
    Abstract: An information processing apparatus that executes an operating system, the apparatus including a panic process unit configured to stop the operating system when the operating system has detected an error, a mapping process unit configured to assign, to the operating system stopped by the panic process unit, a second memory area which is other than a first memory area being used by a kernel of the operating system before stop or by a hypervisor that controls the operating system before stop of the operating system, a reactivation process unit configured to reactivate the operating system by using the second memory area as a usage area, and a memory dump process unit configured to read data in the first memory area, and to write the data to a dump file after the operating system is reactivated.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 21, 2015
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kondou, Kenji Okano
  • Publication number: 20140281343
    Abstract: A processing apparatus includes a plurality of memories and a plurality of processors coupled to the plurality of memories and configured to determine, in accordance with a demand for allocation of a memory area of a first size to store first data used by an operating system, whether or not a memory area of a third size may be secured for each of the plurality of memories, the third size being obtained by adding the memory area of the first size and a memory area of a second size to store data used by an application program, and to store the first data in a first memory among the plurality of memories in a case where the first memory is determined to be capable of securing the memory area of the third size.
    Type: Application
    Filed: January 14, 2014
    Publication date: September 18, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Kondou