Abstract: A display apparatus automatically rounds corners of a rectangular area frame for display thereof, the rectangular area frame including that of a window or that of a graph and the like displayed within the window. The rounding is effected by automatically calculating and displaying circular arcs (ellipstic arcs) of corners based on the inputted corner coordinates of the rectangular area frame, or by not displaying one or several dots of each corner. In the case where multi-windows are displayed in an overlap manner or a plurality of rectangular area frames are displayed within a window, the corners are not displayed stiffly and emphasized unnecessarily, thus providing a visually soft and natural display image, improving the quality of displayed images, and providing an improved handy method for use by an operator.

Abstract: A mobile station, operable in a mobil communication system that executes a location registration processing by using the channel quality of a base station and an information concerning a base station the mobile station includes a base station information memory unit for storing therein information concerning a plurality of base stations and an amount in which the channel quality of the base station is changed with time and a location judging unit for judging on the basis of the amount in which the base station information is changed with time and which is stored in the base station information memory unit whether or not location registration processing is to be executed indicating a location in service area.

Abstract: An intermittenceless switching system includes two speech path memories having sufficient capacity to store a single frame of data having a plurality of time slots. The incoming data is stored in one memory, while the outgoing data is read from the other memory. A control circuit continuously alternates the read/write functions between the two memories. A control memory is used to store switch control information. The system includes a buffer memory that is present between a data processor and the control memory to prevent switch operation during data transmission. The system also includes a monitoring circuit for detecting an indication bit signifying the presence or absence of data in the time slot.

Abstract: A communication system including a plurality of portable terminal apparatuses each capable of calling a partner terminal apparatus via a radio channel and a plurality of fixed terminal apparatuses each being connected via an ISDN interface to a time-division switch and each being connectable to the portable terminal in which when two portable terminals having an established cell are respectively attached to two fixed terminal apparatuses arbitrarily selected, the state of the call is automatically transferred to the two fixed terminal apparatuses so that the speech can be achieved between the fixed terminal apparatuses without conducting another call establishing procedure.

Abstract: This invention proposes a radio communication system including a plurality of radio terminals, a relay apparatus (including a plurality of base stations and an exchange station) connected to each radio terminal so that the radio terminals can interchange information from each other, and a data processing unit connected to the relay apparatus, each radio terminal having a circuit for inputting and outputting a voice signal and a circuit for inputting and outputting data whereby it can communicate with another radio terminals or with the data processing unit through the relay apparatus. The radio terminal of this invention further has a clock, and a circuit for storing a schedule inputted by the user thereby to automatically select a receiving mode such as a ringing mode or a nonringing mode in accordance with the contents of the schedule, the present time and so on.

Abstract: When the subscribers are connected with the switching system by the optical fibers, in order to realize the signal exchange without converting the optical signals sent by the optical fibers into the electric signal, the optical switching system is constituted by: an optical time division multiplexer for time division multiplexing the optical signals which were sent by a plurality of fiber optic cables corresponding to a plurality of subscribers; an optical time switch for changing the time arrangement of the output signals of the optical time division multiplexer; and an optical time division demultiplexer for distributing the time sequential signal of the output signals of the optical time switch to the optical fibers of a plurality of subscriber lines.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunkline, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.

Abstract: In a packet exchange system for preforming packet exchange by setting logical channels, individual input packets are assigned with information indicative of input sequence of the individual input packets counted in each call and the input sequence information is stored. Each time each packet is delivered, the input sequence information assigned to an input packet is stored as an output sequence information in a call to which the delivered packet belongs, and the status of congestion of packets of the call which are present in the exchange is decided on the basis of the stored input sequence information and output sequence information.

Abstract: A fixed-length packet switching system, in which fixed-length packets (cells) each composed of a header portion and a data portion are received from a plurality of input lines, and after conversion of the header portions, the received packets are transmitted onto selected ones of output lines designated by their header portions.

Abstract: A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.

Abstract: In duplicated equipment including main equipment, duplicated subordinate equipment, and a communication line for transferring data between the main equipment and the duplicated subordinate equipment and for sending a changeover signal which can put one and the other of a pair of subordinate devices making up the duplicated subordinate equipment in an active state and a standby state, respectively, from the main equipment to the duplicated subordinate equipment, each of the subordinate devices includes means for putting the other subordinate device in the standby state, to prevent both of the subordinate devices from being put in the active state when a failure occurs on a transmission path between the communication line and one of the subordinate devices.

Abstract: This invention relates to a time division switching system for exchanging audio signals, data and so on in a time division manner. This time division switchboard comprises a plurality of separate local exchange units capable of interfacing with various different circuits such as subscriber lines, trunk lines, service circuits and so on, one or a plurality of junctor high ways connected to a time switch of each of the local exchange units, and one or a plurality of tandem exchange units each having a time switch connected to the other ends of the junctor high ways and switching by the time switch. Each of the local exchange units selects a channel on an arbitrary junctor high way and transmits control information concerning other one of the local exchange units to which a calling is to be sent, to one of the tandem exchange units which has the selected junctor high way connected thereto.

Abstract: In an interface circuit which couples a two-wire line of bidirectional transmission and unidirectional four-wire receiving and transmitting lines; in order to permit the interface circuit to operate in adaptation to the fluctuation of an impedance with the two-wire line side viewed from the four-wire receiving line, the four-wire receiving line is provided with a plurality of filters and a group of switches for selecting the filters, an output of the four-wire transmitting line is compared with outputs obtained by scanning the filters, and the filter providing the minimum output difference in the comparisons is selected and connected.

Abstract: A time-division switching unit for connecting a desired channel of a desired one of a plurality of input highways to a desired channel of a desired one of a plurality of output highways is disclosed. A frame synchronization circuit of the time-division switching unit variably delays signals of the input highways within one channel period, writes the signals to a speech memory for each channel, modifies write addresses to the speech memory to attain frame synchronization, extracts frame synchronization signals of the respective highways from the input and output of the speech memory, and controls the amount of delay within one channel period and the amount of address modification by the extracted synchronization signals.

Abstract: In a convergence distortion correction method and apparatus for raster-scanned color CRT having a dynamic convergence magnet assembly, the CRT display screen is divided into a plurality of zones. A digital memory is provided with a data storage field and a flag bit field at each address. Addresses of the zones are generated by means of a sync signal regenerated from an input video signal. First, the addresses of zones to be subjected to the adjustment of convergence distortion are selected to set flags in the flag bit fields of the digital memory at its addresses specified by the selected zone addresses. Then, by referring to the flags, guide patterns are displayed on the selected zones and are used to adjust the convergence distortions in those zones. Preferably, one of the displayed guide patterns is flickered. Correction data based on the results of the adjustment are stored in the data storage fields of the digital memory at the corresponding addresses.

Abstract: Disclosed is an optical switch of the rotary-type in which a pair of opposing optical transmission path mounting members are disposed on the same axis.A plurality of junction faces of optical transmission paths disposed on the respective opposing plane portions of the mounting members along phantom circles which are opposite to each other and concentric with the pair of mounting members respectively with respect to the axis so that the junction faces on the respective plane portions are capable of being correspondingly opposite to each other.When the pair of the mounting members are relatively rotated about the axis, the facing mates of the opposing junction faces of the optical transmission paths are changed over to switch the optical transmission paths.In the case where an optical path relay member is interposed between the pair of the optical transmission path mounting members, the optical transmission paths can be switched by only the rotation of the optical path relay member.

Abstract: A digital differential analyzer (DDA) is connected through a direct memory access bus (DMA bus) to a host processor so as to receive an operation defining parameter and data, thereby to process a differential analysis as a digital operation.The DDA has mainly an arithmetic processor for DDA operation, and a control processor for performing the control concerning DMA to the host processor and the start and end control of the DDA operation which is performed by the arithmetic processor. This DDA decreases the amount of program to be processed by the host processor.

Abstract: A recursive-type digital filter comprising a calculation circuit. The calculation circuit is arranged to multiply an input signal including at least m-bit signal x.sub.n inputted at a predetermined sampling period and an output signal y.sub.n-k fed back to the input of the calculation circuit in accordance with the input signal x.sub.n after being subjected to a delay of k sampling periods by a.sub.k and b.sub.k coefficients corresponding to the filter characteristics, respectively, and then the products are added thereby to produce data y.sub.n of (m+l) bits satisfying, ##EQU1## and serially deliver the upper m-bit data of the data y.sub.n as an output signal corresponding to the input signal x.sub.n.The filter further comprises a delay circuit for feeding back to the input of the calculation circuit a part of the round off data including the upper (m+1)th bit of the data y.sub.n so that the b.sub.k coefficient is multiplied by the fedback data of the upper (m+1)th bit and the product is added to the data y.

Abstract: A recursive type digital filter receiving a digital input signal x(n) having a plurality of bits and delivering a ditial output signal y(n) satisfying the following equation, ##EQU1## where n indicates a natural number, M and N orders of time lag in the signal transference, a.sub.k and b.sub.k coefficients defined by a filter characteristic, a.sub.M and b.sub.N b being coefficients which are not equal to zero, comprises an output control circuit for delivering a digital signal indicating a positive or negative limit value in place of the digital output signal y(n) when the amplitude of the signal y(n) exceeds an allowable value. In combination with this output control circuit, the filter also utilizes a feedback signal for calculation purposes which feedback signal has its amplitude reduced from that of y(n) by a predetermined ratio. Further, an arrangement is provided for clearing registers of filter when necessary to prevent overflow oscillation.

Abstract: A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.