Patents by Inventor Hiroshi Masai

Hiroshi Masai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10332681
    Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 25, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masaki Tsukida, Hiroshi Masai
  • Publication number: 20190027310
    Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 24, 2019
    Inventors: Masaki TSUKIDA, Hiroshi MASAI
  • Patent number: 10109420
    Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: October 23, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masaki Tsukida, Hiroshi Masai
  • Patent number: 10074479
    Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 11, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masaki Tsukida, Hiroshi Masai
  • Patent number: 9947471
    Abstract: A multilayer capacitor includes a multilayer body with sides each about 0.3 mm or smaller when viewed from a stacking direction of the multilayer body, and first and second outer electrodes disposed on a surface of the multilayer body. An outermost one of the conductive layers is bent to be convex in the stacking direction and includes penetrating portions extending in the stacking direction. In a cross section perpendicular or substantially perpendicular to a lengthwise direction of the multilayer body, assuming the bent conductive layer is equally divided into four regions named region A, region B, region C, and region D arranged in the order named in a widthwise direction of the multilayer body, a sum of minimum diameters of the penetrating portions is larger in the region A than in the region B and larger in the region D than in the region C.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: April 17, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masaki Tsukida, Hiroshi Masai
  • Publication number: 20180075969
    Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
    Type: Application
    Filed: November 3, 2017
    Publication date: March 15, 2018
    Inventors: Masaki TSUKIDA, Hiroshi MASAI
  • Patent number: 9911534
    Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: March 6, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masaki Tsukida, Hiroshi Masai
  • Publication number: 20180053600
    Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
    Type: Application
    Filed: November 3, 2017
    Publication date: February 22, 2018
    Inventors: Masaki TSUKIDA, Hiroshi MASAI
  • Publication number: 20160247632
    Abstract: A multilayer capacitor includes a multilayer body with sides each about 0.3 mm or smaller when viewed from a stacking direction of the multilayer body, and first and second outer electrodes disposed on a surface of the multilayer body. An outermost one of the conductive layers is bent to be convex in the stacking direction and includes penetrating portions extending in the stacking direction. In a cross section perpendicular or substantially perpendicular to a lengthwise direction of the multilayer body, assuming the bent conductive layer is equally divided into four regions named region A, region B, region C, and region D arranged in the order named in a widthwise direction of the multilayer body, a sum of minimum diameters of the penetrating portions is larger in the region A than in the region B and larger in the region D than in the region C.
    Type: Application
    Filed: February 3, 2016
    Publication date: August 25, 2016
    Inventors: Masaki TSUKIDA, Hiroshi MASAI
  • Publication number: 20160155569
    Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
    Type: Application
    Filed: November 17, 2015
    Publication date: June 2, 2016
    Inventors: Masaki TSUKIDA, Hiroshi MASAI
  • Patent number: 4654306
    Abstract: A novel species of acetic acid bacteria belonging to the genus of Acetobacter, to which a scientific name of Acetobacter altoacetigenes MH-24 (FERM BP-491) is given. The bacteria can grow in a culture medium containing at least 4 w/v % of acetic acid with a pH of 3.5 at the highest. Pure samples of species have been isolated and used for the fermentation production of vinegar without undertaking the conventional inoculation process using the prior art seed vinegar to provide a high-quality vinegar of high acetic acid concentration such as white vinegar, with high production efficiency.
    Type: Grant
    Filed: February 21, 1985
    Date of Patent: March 31, 1987
    Assignee: Nakano Vinegar Co., Ltd.
    Inventors: Etsuzo Entani, Seiichi Fujiyama, Shoji Ohmori, Hiroshi Masai
  • Patent number: 4575551
    Abstract: Novel highly viscous acidic heterpolysaccharide AM-2 is produced from a strain of genus Acetobacter isolated from vinegar mash, and is useful as an adhesive, coating agent, drilling mud additive, enhanced oil recovering agent, etc., as well as a material useful for the production of foods, drugs and cosmetics because of its safety and high viscosity.
    Type: Grant
    Filed: October 25, 1983
    Date of Patent: March 11, 1986
    Assignee: Nakano Vinegar Co., Ltd.
    Inventors: Seiichi Fujiyama, Hiroyuki Minakami, Kenji Tayama, Hiroshi Masai
  • Patent number: 4514563
    Abstract: Novel highly viscous polysaccharides composed mainly of (a) glucose, (b) galactose, (c) mannose, and (d) glucuronic acid, the molar ratio of (a):(b):(c):(d) being 10:3-6:0.5-2:0.5-2 (preferably 10:3-4:1-2:1-2). The invention also provides the process for producing the highly viscous polysaccharides which comprises cultivating a highly viscous polysaccharide-producing microorganism which is an acetic acid bacteria in a nutrient medium until a substantial amount of polysaccharides has accumulated in the nutrient medium, and recovering the accumulated polysaccharides from the nutrient medium.
    Type: Grant
    Filed: March 29, 1983
    Date of Patent: April 30, 1985
    Assignee: Nakano Vinegar Co., Ltd.
    Inventors: Seiichi Fujiyama, Hiroyuki Minakami, Hiroshi Masai
  • Patent number: 4378375
    Abstract: Vinegar having an acetic acid concentration higher than 20 percent weight by volume is produced in a submerged fermentation by maintaining the temperature of a fermenting broth at 27.degree.-32.degree. C. until the acetic acid concentration of the fermenting broth (after the initiation of fermentation) reaches 12-15 percent weight by volume. Then the temperature of the fermenting broth is lowered by 0.5.degree. C. to 2.degree. C. Fermentation is continued at the lower temperature until the concentration of acetic acid increases by between 0.05 to 2 percent weight by volume. At this time, the temperature is again reduced by from 0.5.degree. C. to 2.degree. C. The fermentation is continued, with subsequent temperature reductions of from 0.5.degree. C. to 2.degree. C. each time that the concentration of acetic acid in the fermentation broth increases by 0.
    Type: Grant
    Filed: October 10, 1980
    Date of Patent: March 29, 1983
    Assignee: Nakano Vinegar Co., Ltd.
    Inventors: Yoshio Kunimatsu, Shoji Ohmori, Hiroshi Masai, Koki Yamada, Mikio Yamada
  • Patent number: 4364960
    Abstract: A finished vinegar having an acetic acid concentration higher than 20 percent weight by volume is produced by repeating a fermentation cycle wherein a broth is fermented at 27.degree.-32.degree. C. in a 1st submerged fermentation tank by a continuous batch process, and, when the acetic acid concentration of the fermenting broth reaches 12-15 percent weight by volume, the large part of the fermenting broth in the 1st fermentation tank is withdrawn and charged in a 2nd submerged fermentation tank. The 1st fermentation tank is recharged with a mash and the fermentation of the fermenting broth in the 2nd tank is continued under aeration while lowering the temperature of the fermenting broth in such manner that the final fermentation temperature does not fall below 18.degree. C. and the lowering temperature does not become higher than the temperature once lowered.
    Type: Grant
    Filed: September 30, 1980
    Date of Patent: December 21, 1982
    Assignee: Nakano Vinegar Co., Ltd.
    Inventors: Yoshio Kunimatsu, Hajime Okumura, Hiroshi Masai, Koki Yamada, Mikio Yamada
  • Patent number: 4282257
    Abstract: Vinegar having an acetic acid concentration higher than 18 percent weight by volume is produced in a submerged fermentation by maintaining the temperature of the fermenting broth after the initiation of the fermentation at 27.degree.-32.degree. C. until the acetic concentration of the fermenting broth reaches 12-15 percent weight by volume and thereafter maintaining the temperature of the fermenting broth at 18.degree.-24.degree. C.
    Type: Grant
    Filed: January 25, 1980
    Date of Patent: August 4, 1981
    Assignee: Nakano Vinegar Co., Ltd.
    Inventors: Yoshio Kunimatsu, Hajime Okumura, Hiroshi Masai, Koki Yamada, Mikio Yamada
  • Patent number: 4241095
    Abstract: A method for preserving soy sauce which comprises admixing therewith acetic acid and a salt of acetic acid, propionic acid, butyric acid, malic acid, tartaric acid, citric acid or lactic acid. The amount of the acid salt is in excess of the amount of acetic acid. The method provides a sufficient antiseptic effect without producing a sour taste and without greatly lowering the pH.
    Type: Grant
    Filed: December 4, 1978
    Date of Patent: December 23, 1980
    Assignee: Nakano Vinegar Co., Ltd.
    Inventors: Kunihiko Shibata, Genji Yamaguchi, Kimio Takeda, Hiroshi Masai