Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit lines coupled to the selection transistor; a selection gate line driver circuit; a control gate line driver circuit; and a source line driver circuit, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprises a second transistor including second gate insulation films and drives the control gate line and the source line with a boost voltage higher than the first driving voltage.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit lines coupled to the selection transistor; a selection gate line driver circuit; a control gate line driver circuit; and a source line driver circuit, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprises a second transistor including second gate insulation films and drives the control gate line and the source line with a boost voltage higher than the first driving voltage.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit lines coupled to the selection transistor; a selection gate line driver circuit; a control gate line driver circuit; and a source line driver circuit, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprise a second transistor including second gate insulation films and drive the control gate line and the source line with a boost voltage higher than the first driving voltage.

Abstract: Nonvolatile evaluation memory cells are programmed to be a plurality of different values in advance, respectively. An internal voltage generating circuit can change the value of an internal voltage according to adjusting signals. To make the internal voltage close to its expected value, a voltage adjusting circuit outputs adjusting signals in accordance with cell currents that flow through the evaluation memory cells, respectively, in a read operation on the evaluation memory cells. As a result, the interval voltage that is shifted from its expected value due to variations in manufacturing conditions can automatically be set to the expected value by using the adjusting signals. Since an internal circuit operates on a correct internal voltage, operation margins can be increased. The yield of a nonvolatile semiconductor memory can thus be increased.

Abstract: A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit lines coupled to the selection transistor; a selection gate line driver circuit; a control gate line driver circuit; and a source line driver circuit, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprise a second transistor including second gate insulation films and drive the control gate line and the source line with a boost voltage higher than the first driving voltage.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A nonvolatile semiconductor memory in which the area of each memory cell is small and which can perform high-speed operation with accuracy. A pair of honeycomb-like diffusion layers which are deviated from each other by a quarter-pitch are formed. Memory transistors (MemoryTr) and select transistors (SelectTr) are formed at portions where a pair of adjacent word lines pass over one diffusion layer and at portions where another pair of adjacent word lines pass over the other diffusion layer. In this case, the memory transistors and the select transistors are arranged so as to form a memory cell between a pair of bit lines connected to each diffusion layer. As a result, though the select transistors are located, many memory cells can be arranged like an array in a small layout area.

Abstract: A nonvolatile semiconductor memory is capable of dual and triple operation with a small chip size. A plurality of sectors is formed. Each sector has nonvolatile memory cells, local bit lines connected to these memory cells, and switch circuits. Write global bit lines and read global bit lines are each wired commonly to the sectors. The write global bit lines transfer write data to the memory cells or verify data from the memory cells. The read global bit lines transfer read data from the memory cells. The switch circuits connect the local bit lines to the write global bit lines or the read global bit lines in accordance with the operation modes. Consequently, it is possible to execute read operation while executing a write sequence or an erase sequence. That is, dual operation can be executed.

Abstract: A nonvolatile semiconductor memory in which the area of each memory cell is small and which can perform high-speed operation with accuracy. A pair of honeycomb-like diffusion layers which are deviated from each other by a quarter-pitch are formed. Memory transistors (MemoryTr) and select transistors (SelectTr) are formed at portions where a pair of adjacent word lines pass over one diffusion layer and at portions where another pair of adjacent word lines pass over the other diffusion layer. In this case, the memory transistors and the select transistors are arranged so as to form a memory cell between a pair of bit lines connected to each diffusion layer. As a result, though the select transistors are located, many memory cells can be arranged like an array in a small layout area.

Abstract: A redundancy substitution method for memory cells within an electrically writable and erasable semiconductor memory device, includes detecting a memory cell having a tendency of a charge loss and/or a charge gain, by use of a charge loss detecting reference cell and/or a charge gain detecting reference cell. The charge loss detecting reference cell has a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell that is higher than that of the read reference cell, and the charge gain detecting reference cell has a threshold value set between the threshold value of the read reference cell and a threshold value of an erase verify reference cell that is lower than that of the read reference cell. The method subjects a memory cell whose tendency of the charge loss and/or the charge gain is detected to a redundancy substitution.

Abstract: Nonvolatile evaluation memory cells are programmed to be a plurality of different values in advance, respectively. An internal voltage generating circuit can change the value of an internal voltage according to adjusting signals. To make the internal voltage close to its expected value,- a voltage adjusting circuit outputs adjusting signals in accordance with cell currents that flow through the evaluation memory cells, respectively, in a read operation on the evaluation memory cells. As a result, the interval voltage that is shifted from its expected value due to variations in manufacturing conditions can automatically be set to the expected value by using the adjusting signals. Since an internal circuit operates on a correct internal voltage, operation margins can be increased. The yield of a nonvolatile semiconductor memory can thus be increased.

Abstract: A redundancy substitution method for memory cells within an electrically writable and erasable semiconductor memory device, includes detecting a memory cell having a tendency of a charge loss and/or a charge gain, by use of a charge loss detecting reference cell and/or a charge gain detecting reference cell. The charge loss detecting reference cell has a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell that is higher than that of the read reference cell, and the charge gain detecting reference cell has a threshold value set between the threshold value of the read reference cell and a threshold value of an erase verify reference cell that is lower than that of the read reference cell. The method subjects a memory cell whose tendency of the charge loss and/or the charge gain is detected to a redundancy substitution.

Abstract: A designing device for designing a layout of a semiconductor device includes a layout position candidate extracting unit for obtaining layout position candidates of a regulator, a tentatively wiring unit for tentatively arranging the regulator at the layout position candidates and tentatively laying out a power line, and a regulator layout position deciding unit for deciding a position of a tentative layout at which an area of the power line that is tentatively laid out is the smallest as the layout position of the regulator.

Abstract: A nonvolatile semiconductor memory is capable of dual and triple operation with a small chip size. A plurality of sectors is formed. Each sector has nonvolatile memory cells, local bit lines connected to these memory cells, and switch circuits. Write global bit lines and read global bit lines are each wired commonly to the sectors. The write global bit lines transfer write data to the memory cells or verify data from the memory cells. The read global bit lines transfer read data from the memory cells. The switch circuits connect the local bit lines to the write global bit lines or the read global bit lines in accordance with the operation modes. Consequently, it is possible to execute read operation while executing a write sequence or an erase sequence. That is, dual operation can be executed.

Abstract: In a flash memory having, for example, a single-gate type memory cell consisting of the gate electrode provided via a thin charge trap layer on a semiconductor substrate, there is provided a non-volatile semiconductor memory that is characterized in applying a short pulse to the memory cell to partly remove the electrons from the charge trap layer after writing the data to the memory cell. This ensures the write operation reliability of non-volatile semiconductor memory such as single-gate type flash memory or the like without changing the basic structure of the memory cell array.

Abstract: An Nch-Tr having a gate connected to an input terminal and an Nch-Tr having a gate connected to an output signal voltage supply terminal through a Pch-Tr are connected to an output terminal for outputting an output signal carrying a second voltage level. In changing the output signal from a high level to a low level in accordance with a change of an input signal carrying a first voltage level, both the Nch-Trs are initially turned ON to lower the voltage of the output signal, and then the Nch-Tr having its gate connected to the output signal voltage supply terminal through the Pch-Tr is brought into a high ON state (a state of higher driving power) to turn the voltage of the output signal to the low level, so that the output signal can be changed quickly by a simple circuit configuration.