Patents by Inventor Hiroshi Miki
Hiroshi Miki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150121372Abstract: The network connection of a VM (target VM) that has been live-migrated from a first physical computer to a second physical computer is restored in a virtual computer system in which communication is performed using a certain type of information outside the jurisdiction of a virtualization mechanism. When receiving a packet from the VM, the first virtualization mechanism of the first physical computer extracts a certain type of information from the packet and registers the extracted certain type of information in a first management information unit. The first virtualization mechanism transmits the certain type of information in the first management information unit to the second virtualization mechanism of the second physical computer during live migration.Type: ApplicationFiled: August 22, 2012Publication date: April 30, 2015Applicant: Hitachi, Ltd.Inventors: Yukari Hatta, Norimitsu Hayakawa, Hiroshi Miki, Shiro Nohara, Takao Totsuka
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Publication number: 20150075971Abstract: System and method of insulating film deposition. A sputter deposition chamber comprises a pair of targets made of the same insulating material. Each target is applied with a high frequency power signal concurrently. A phase adjusting unit is used to adjust the phase difference between the high frequency power signals supplied to the pair of targets to a predetermined value, thereby improving the in-plane thickness distribution of a resultant film. The predetermined value is target material specific.Type: ApplicationFiled: September 18, 2014Publication date: March 19, 2015Inventors: Shinji FURUKAWA, Naoki WATANABE, Hiroshi MIKI, Tooru KITADA, Yasuhiko KOJIMA
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Patent number: 8900426Abstract: A sputtering apparatus including a target holder configured to hold at least two targets; a substrate holder configured to hold a substrate; a first shutter plate arranged between the target holder and the substrate holder, the first shutter plate having at least two holes and being capable of rotating around an axis; a second shutter plate arranged between the first shutter plate and the substrate holder, the second shutter plate having at least two holes and being capable of rotating around the axis; wherein the first and second shutter plates are rotated such that paths are simultaneously created between the at least two targets and the substrate through the at least two holes of the rotated first shutter plate and the at least two holes of the rotated second shutter plate, and a film is formed on the substrate by co-sputtering of the at least two targets.Type: GrantFiled: December 12, 2011Date of Patent: December 2, 2014Assignee: Canon Anelva CorporationInventors: Shuji Nomura, Ayumu Miyoshi, Hiroshi Miki
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Publication number: 20140059302Abstract: A hypervisor as a movement source stores key information, and the key information is registered in a storage using the stored key information through a logical HBA which is used for migration.Type: ApplicationFiled: August 1, 2013Publication date: February 27, 2014Applicant: HITACHI, LTD.Inventors: Norimitsu HAYAKAWA, Eiichiro OIWA, Yukari HATTA, Hiroshi MIKI, Takuji TERAYA
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Publication number: 20120097533Abstract: A sputtering apparatus including a target holder configured to hold at least two targets; a substrate holder configured to hold a substrate; a first shutter plate arranged between the target holder and the substrate holder, the first shutter plate having at least two holes and being capable of rotating around an axis; a second shutter plate arranged between the first shutter plate and the substrate holder, the second shutter plate having at least two holes and being capable of rotating around the axis; wherein the first and second shutter plates are rotated such that paths are simultaneously created between the at least two targets and the substrate through the at least two holes of the rotated first shutter plate and the at least two holes of the rotated second shutter plate, and a film is formed on the substrate by co-sputtering of the at least two targets.Type: ApplicationFiled: December 12, 2011Publication date: April 26, 2012Applicant: CANON ANELVA CORPORATIONInventors: Shuji NOMURA, Ayumu Miyoshi, Hiroshi Miki
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Patent number: 8155905Abstract: A method and apparatus for extracting a time constant from a time series of values of a signal that varies in accordance with multiple charge carrier trap defects that cause Random Telegraph Noise (RTN), using transition-based assignment of states.Type: GrantFiled: July 21, 2009Date of Patent: April 10, 2012Assignee: Hitachi, Ltd.Inventor: Hiroshi Miki
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Publication number: 20110022339Abstract: A method and apparatus for extracting a time constant from a time series of values of a signal that varies in accordance with multiple charge carrier trap defects that cause Random Telegraph Noise (RTN), using transition-based assignment of states.Type: ApplicationFiled: July 21, 2009Publication date: January 27, 2011Inventor: Hiroshi MIKI
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Patent number: 7850827Abstract: A double-layer shutter control method of a multi-sputtering system provided with three targets in a single chamber and a double-layer rotating shutter mechanism having shutter plates which independently rotate and have holes formed therein, comprising selecting a target by a combination of holes of a first shutter plate and a second shutter plate and uses the selected target for a pre-sputtering step and a main sputtering step with continuous discharge so as to deposit a film on a substrate, whereby it is possible to prevent cross-contamination between targets due to target substances etc. deposited on the shutter plates.Type: GrantFiled: March 14, 2005Date of Patent: December 14, 2010Assignee: Canon Anelva CorporationInventors: Shuji Nomura, Ayumu Miyoshi, Hiroshi Miki
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Patent number: 7728376Abstract: HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.Type: GrantFiled: March 21, 2007Date of Patent: June 1, 2010Assignee: Hitachi, Ltd.Inventors: Yuichi Matsui, Hiroshi Miki
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Patent number: 7709315Abstract: An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d?0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.Type: GrantFiled: July 5, 2007Date of Patent: May 4, 2010Assignee: Renesas Technology Corp.Inventors: Naoki Tega, Hiroshi Miki, Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru
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Publication number: 20090230510Abstract: A rutile phase can be formed even in the case of a thin film by adding nickel or cobalt to titanium dioxide in the range of 0.5 to 10 atm %, and the use of this element-added titanium dioxide film in a capacitor dielectric film results in an increase in capacitance per unit area of a DRAM memory cell and enables a high-integration DRAM to be realized at low cost.Type: ApplicationFiled: March 9, 2009Publication date: September 17, 2009Applicant: Elpida Memory, Inc.Inventors: Hiroshi Miki, Tomoko Sekiguchi, Naomi Inada, Mitsuhiro Horikawa
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Publication number: 20090139865Abstract: A double-layer shutter control method of a multi-sputtering system provided with three targets in a single chamber and a double-layer rotating shutter mechanism having shutter plates which independently rotate and have holes formed therein, comprising selecting a target by a combination of holes of a first shutter plate and a second shutter plate and uses the selected target for a pre-sputtering step and a main sputtering step with continuous discharge so as to deposit a film on a substrate, whereby it is possible to prevent cross-contamination between targets due to target substances etc. deposited on the shutter plates.Type: ApplicationFiled: November 17, 2008Publication date: June 4, 2009Applicant: Canon Anelva CorporationInventors: Shuji Nomura, Ayumu Miyoshi, Hiroshi Miki
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Publication number: 20080157157Abstract: A DRAM capacitor uses ruthenium or ruthenium oxide as an upper electrode and hafnium dioxide or zirconium oxide as an insulation layer. The DRAM capacitor is intended to suppress diffusion of ruthenium, etc. into hafnium dioxide. Tantalum pentoxide or niobium oxide having a higher permittivity than that of the insulation layer is inserted as a cap insulation layer to the boundary between the upper electrode of ruthenium or ruthenium oxide and the insulation layer of hafnium dioxide or zirconium oxide to thereby suppress diffusion of ruthenium, etc. into hafnium dioxide, etc.Type: ApplicationFiled: November 15, 2007Publication date: July 3, 2008Inventors: Osamu TONOMURA, Hiroshi MIKI, Tomoko SEKIGUCHI, Kenichi TAKEDA
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Patent number: 7364965Abstract: A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused. Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.Type: GrantFiled: November 12, 2004Date of Patent: April 29, 2008Assignee: Hitachi, Ltd.Inventors: Osamu Tonomura, Hiroshi Miki, Yuichi Matsui, Tomoko Sekiguchi, Kikuo Watanabe
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Publication number: 20080048249Abstract: An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d?0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.Type: ApplicationFiled: July 5, 2007Publication date: February 28, 2008Inventors: NAOKI TEGA, Hiroshi Miki, Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru
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Publication number: 20070257295Abstract: A capacitance of a capacitor including a metal electrode is increased by using a dielectric film having a high dielectric constant. A band gap is reduced as the dielectric constant of a material is increased. In a dielectric having the dielectric constant of 50 or more such as strontium titanate, the high dielectric constant is ensured due to the crystallization but the side effect of the increased leakage current occurs. Since the replacement of the material requires the significant change of the manufacturing apparatus or the manufacturing process, the manufacturing cost is increased. Hafnium oxide is not replaced with the other materials, but the dielectric constant of hafnium oxide is improved to increase the capacitance. An element having a large ion radius such as yttrium is added in a small amount to increase the dielectric constant of hafnium while an amorphous state is maintained. The capacitor process where the amorphous state is maintained is applied to produce the DRAM at low cost.Type: ApplicationFiled: March 5, 2007Publication date: November 8, 2007Inventors: Hiroshi Miki, Yuichi Matsui
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Publication number: 20070254877Abstract: The present invention relates to a compound represented by the formula wherein A is a benzene ring optionally having substituents, R1, R2a and R3 are each a hydrogen atom, a hydrocarbon group optionally having substituents or a heterocyclic group optionally having substituents, R1 and R2a may form a ring via X, when R1 and R2a form a ring via X, R1 and R2a are each a bond or a divalent C1-5 acyclic hydrocarbon group optionally having substituents, and X is a bond, an oxygen atom, an optionally oxidized sulfur atom or an imino group optionally having a substituent, provided that R1, R2a and X are not bonds at the same time, or a salt thereof, and an agent for inhibiting kinase (phosphorylation enzyme), which contains this compound or a prodrug thereof. The compound of the present invention has an inhibitory activity against kinase such as a vascular endothelial growth factor receptor (VEGFR) and the like, and is useful as an agent for the prophylaxis or treatment of cancer and the like.Type: ApplicationFiled: June 1, 2005Publication date: November 1, 2007Applicant: Takada Pharmaceutical Company LimitedInventors: Yuji Nishikimi, Hideto Fukushi, Hiroshi Miki
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Publication number: 20070228427Abstract: HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.Type: ApplicationFiled: March 21, 2007Publication date: October 4, 2007Inventors: Yuichi Matsui, Hiroshi Miki
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Patent number: 7256437Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.Type: GrantFiled: August 18, 2004Date of Patent: August 14, 2007Assignee: Renesas Technology Corp.Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
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Patent number: 7247890Abstract: Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.Type: GrantFiled: September 1, 2004Date of Patent: July 24, 2007Assignee: Hitachi, Ltd.Inventors: Tomoko Sekiguchi, Shinichiro Kimura, Renichi Yamada, Kikuo Watanabe, Hiroshi Miki, Kenichi Takeda