Patents by Inventor Hiroshi Minakata
Hiroshi Minakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10580783Abstract: A three-dimensional memory device includes a first-tier structure containing a first alternating stack of first insulating layers and first electrically conductive layers that has first stepped surfaces, and a first retro-stepped dielectric material portion contacting the first stepped surfaces of the first alternating stack, and a second-tier structure containing a second alternating stack of second insulating layers and second electrically conductive layers that has second stepped surfaces, and a second retro-stepped dielectric material portion contacting the second stepped surfaces of the second alternating stack. The first retro-stepped dielectric material portion has a higher etch rate than the second retro-stepped dielectric material portion. Memory stack structures vertically extend through the first alternating stack and the second alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel.Type: GrantFiled: March 1, 2018Date of Patent: March 3, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhixin Cui, Hiroshi Minakata, Keigo Kitazawa, Yoshiyuki Okura
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Publication number: 20190273088Abstract: A three-dimensional memory device includes a first-tier structure containing a first alternating stack of first insulating layers and first electrically conductive layers that has first stepped surfaces, and a first retro-stepped dielectric material portion contacting the first stepped surfaces of the first alternating stack, and a second-tier structure containing a second alternating stack of second insulating layers and second electrically conductive layers that has second stepped surfaces, and a second retro-stepped dielectric material portion contacting the second stepped surfaces of the second alternating stack. The first retro-stepped dielectric material portion has a higher etch rate than the second retro-stepped dielectric material portion. Memory stack structures vertically extend through the first alternating stack and the second alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Inventors: Zhixin CUI, Hiroshi MINAKATA, Keigo KITAZAWA, Yoshiyuki OKURA
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Patent number: 10192784Abstract: An alternating stack of insulating layers and sacrificial material layers including stepped surfaces is formed over a substrate. After formation of a retro-stepped dielectric material portion over the stepped surfaces, an array of cylindrical openings is formed through the retro-stepped dielectric material portion and the alternating stack. A continuous cavity is formed by isotropically etching the insulating layers and the retro-stepped dielectric material portion selective to the sacrificial material layers. Remaining portions of the retro-stepped dielectric material portion include dielectric pillar structures. A continuous fill material portion is formed in the continuous cavity. Memory stack structures are formed through the alternating stack. The sacrificial material layers and the dielectric pillar structures are replaced with combinations of an electrically conductive layer and a contact via structure. The contact via structures are self-aligned to the electrically conductive layers.Type: GrantFiled: February 22, 2018Date of Patent: January 29, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhixin Cui, Hiroshi Minakata, Keigo Kitazawa, Yoshiyuki Okura
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Publication number: 20100178744Abstract: An insulating film having Hf and O is formed over a semiconductor substrate. A cap film having oxygen and titanium as constituent elements is formed over the insulating film. The insulating film and cap film are thermally treated in a nitrogen gas or noble gas to diffuse titanium in the cap film into the insulating film to form a gate insulating film. A gate electrode film is formed over the gate insulating film.Type: ApplicationFiled: December 23, 2009Publication date: July 15, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Haruhiko Takahashi, Hiroshi Minakata, Naoyoshi Tamura
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Patent number: 7741684Abstract: The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1-xOy (0.7<x<1) formed over a semiconductor substrate, and a second dielectric film different from the first dielectric film formed over the first dielectric film; and a gate electrode formed over the gate insulating film and including a polycrystalline silicon film, whereby the local abnormal growth of the polycrystalline silicon film in the process of forming the polycrystalline silicon film is prevented, and the gate leakage current can be much decreased.Type: GrantFiled: July 19, 2005Date of Patent: June 22, 2010Assignee: Fujitsu LimitedInventors: Chikako Yoshida, Hiroshi Minakata, Masaomi Yamaguchi, Shinji Miyagaki, Yasuyuki Tamura
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Patent number: 7521325Abstract: A permeation preventing film of a silicon nitride film 16 is inserted between a silicon substrate 10 and a High-k gate insulation film 18 to thereby prevent the High-k gate insulation film 18 from being deprived of oxygen, while oxygen anneal is performed after a gate electrode layer 20 has been formed to thereby supplement oxygen. The silicon nitride film 16, which is the permeation preventing film, becomes a silicon oxide nitride film 17 without changing the film thickness, whereby characteristics deterioration of the High-k gate insulation film 18 due to the oxygen loss can be prevented without lowering the performance of the transistor. The semiconductor device having the gate insulation film formed of even a high dielectric constant material can be free from the shift of the threshold voltage.Type: GrantFiled: July 28, 2005Date of Patent: April 21, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tsunehisa Sakoda, Masaomi Yamaguchi, Hiroshi Minakata, Yoshihiro Sugita, Kazuto Ikeda
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Patent number: 7470595Abstract: A tight contact layer is disposed on a semiconductor substrate, the tight contact layer being made of one material selected from the group consisting of refractory metal, alloy of refractory metal, nitride of refractory metal, and siliconized nitride of refractory metal. An oxide surface layer is disposed on the surface of the tight contact layer, the oxide surface layer being made of oxide of material constituting the tight contact layer. A first conductive layer is disposed on the surface of the oxide surface layer, the first conductive layer being made of a platinum group or alloy which contains a platinum group. When a conductive layer made of metal such as a platinum group is formed on a tight contact layer, coverage and morphology can be prevented from being degraded.Type: GrantFiled: August 2, 2006Date of Patent: December 30, 2008Assignee: Fujitsu LimitedInventors: Nobuyuki Nishikawa, Hiroshi Minakata, Kouji Tsunoda, Eiji Yoshida
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Publication number: 20080265337Abstract: A semiconductor device fabrication method for forming a gate insulating film of a low leakage transistor and a gate insulating film of a high performance transistor. A first SiON film is formed over a Si substrate through first film formation. The first SiON film is left where the low leakage transistor is to be formed, and is removed where the high performance transistor is to be formed. Through second film formation, a second SiON film is formed where the first SiON film is removed, and a third SiON film including the first SiON film is formed where the first SiON film is left. The formed first SiON film has thickness and nitrogen concentration so that the third SiON film has thickness and nitrogen concentration to be the gate insulting film of the low leakage transistor.Type: ApplicationFiled: July 9, 2008Publication date: October 30, 2008Applicant: FUJITSU LIMITEDInventor: Hiroshi MINAKATA
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Publication number: 20080200000Abstract: After the formation of element isolation insulating films, an n-well, and a p-well on a Si substrate, the Si substrate is subjected to cleaning (step S1) as pretreatment. The surface of the Si substrate is thermally oxidized by rapid thermal oxidation (RTO) to form a silicon oxide film (step S2) as an underlying oxide film. The silicon oxide film is subjected to plasma nitridation (step S3). The plasma nitridation results in the nitridation of the silicon oxide film by the introduction of active nitrogen to form a silicon oxynitride film. Annealing is performed in an ammonia atmosphere (step S4) to further introduce nitrogen into a region near the surface of the silicon oxynitride film. Annealing as post-annealing (step S5) is performed in an atmosphere containing nitrogen and oxygen.Type: ApplicationFiled: February 15, 2008Publication date: August 21, 2008Applicant: FUJITSU LIMITEDInventor: Hiroshi MINAKATA
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Patent number: 7265401Abstract: A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon oxide, above the interface layer; (c) forming a gate electrode of polysilicon above the high dielectric constant gate insulating film; (d) passivating the substrate surface at least before or after the high dielectric constant gate insulating film is formed; (e) forming an insulated gate electrode structure by patterning at least the gate electrode and the high dielectric constant gate insulating film; and (f) forming source/drain regions in the active region on both sides of the insulated gate electrode structure. The semiconductor device has the high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide.Type: GrantFiled: June 9, 2005Date of Patent: September 4, 2007Assignee: Fujitsu LimitedInventors: Masaomi Yamaguchi, Hiroshi Minakata, Tsunehisa Sakoda, Kazuto Ikeda
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Publication number: 20060286744Abstract: A tight contact layer is disposed on a semiconductor substrate, the tight contact layer being made of one material selected from the group consisting of refractory metal, alloy of refractory metal, nitride of refractory metal, and siliconized nitride of refractory metal. An oxide surface layer is disposed on the surface of the tight contact layer, the oxide surface layer being made of oxide of material constituting the tight contact layer. A first conductive layer is disposed on the surface of the oxide surface layer, the first conductive layer being made of a platinum group or alloy which contains a platinum group. When a conductive layer made of metal such as a platinum group is formed on a tight contact layer, coverage and morphology can be prevented from being degraded.Type: ApplicationFiled: August 2, 2006Publication date: December 21, 2006Applicant: FUJITSU LIMITEDInventors: Nobuyuki Nishikawa, Hiroshi Minakata, Kouji Tsunoda, Eiji Yoshida
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Publication number: 20060214243Abstract: A permeation preventing film of a silicon nitride film 16 is inserted between a silicon substrate 10 and a High-k gate insulation film 18 to thereby prevent the High-k gate insulation film 18 from being deprived of oxygen, while oxygen anneal is performed after a gate electrode layer 20 has been formed to thereby supplement oxygen. The silicon nitride film 16, which is the permeation preventing film, becomes a silicon oxide nitride film 17 without changing the film thickness, whereby characteristics deterioration of the High-k gate insulation film 18 due to the oxygen loss can be prevented without lowering the performance of the transistor. The semiconductor device having the gate insulation film formed of even a high dielectric constant material can be free from the shift of the threshold voltage.Type: ApplicationFiled: July 28, 2005Publication date: September 28, 2006Applicant: FUJITSU LIMITEDInventors: Tsunehisa Sakoda, Masaomi Yamaguchi, Hiroshi Minakata, Yoshihiro Sugita, Kazuto Ikeda
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Publication number: 20060214244Abstract: In the method for fabricating a semiconductor device, a polysilicon film is patterned to form a gate electrode 16, and a high dielectric constant insulating film 14 on a silicon substrate 10 and a device isolation film 12 on both sides of the gate electrode 16 is removed by dry etching using plasmas of a mixed gas of a base protection gas which combines with silicon to form a protection layer for protecting the silicon substrate 10 and the device isolation film 12, and an etching gas for etching the high dielectric constant insulating film 14.Type: ApplicationFiled: August 8, 2005Publication date: September 28, 2006Applicant: FUJITSU LIMITEDInventor: Hiroshi Minakata
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Patent number: 7102189Abstract: A tight contact layer is disposed on a semiconductor substrate, the tight contact layer being made of one material selected from the group consisting of refractory metal, alloy of refractory metal, nitride of refractory metal, and siliconized nitride of refractory metal. An oxide surface layer is disposed on the surface of the tight contact layer, the oxide surface layer being made of oxide of material constituting the tight contact layer. A first conductive layer is disposed on the surface of the oxide surface layer, the first conductive layer being made of a platinum group or alloy which contains a platinum group. When a conductive layer made of metal such as a platinum group is formed on a tight contact layer, coverage and morphology can be prevented from being degraded.Type: GrantFiled: December 29, 2003Date of Patent: September 5, 2006Assignee: Fujitsu LimitedInventors: Nobuyuki Nishikawa, Hiroshi Minakata, Kouji Tsunoda, Eiji Yoshida
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Publication number: 20060172498Abstract: A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon oxide, above the interface layer; (c) forming a gate electrode of polysilicon above the high dielectric constant gate insulating film; (d) passivating the substrate surface at least before or after the high dielectric constant gate insulating film is formed; (e) forming an insulated gate electrode structure by patterning at least the gate electrode and the high dielectric constant gate insulating film; and (f) forming source/drain regions in the active region on both sides of the insulated gate electrode structure. The semiconductor device has the high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide.Type: ApplicationFiled: June 9, 2005Publication date: August 3, 2006Applicant: FUJITSU LIMITEDInventors: Masaomi Yamaguchi, Hiroshi Minakata, Tsunehisa Sakoda, Kazuto Ikeda
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Publication number: 20050247988Abstract: The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1-xOy (0.7<x<1) formed over a semiconductor substrate, and a second dielectric film different from the first dielectric film formed over the first dielectric film; and a gate electrode formed over the gate insulating film and including a polycrystalline silicon film, whereby the local abnormal growth of the polycrystalline silicon film in the process of forming the polycrystalline silicon film is prevented, and the gate leakage current can be much decreased.Type: ApplicationFiled: July 19, 2005Publication date: November 10, 2005Applicant: FUJITSU LIMITEDInventors: Chikako Yoshida, Hiroshi Minakata, Masaomi Yamaguchi, Shinji Miyagaki, Yasuyuki Tamura
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Patent number: 6946351Abstract: The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1?xOy (0.7<x<1) formed over a semiconductor substrate, and a second dielectric film different from the first dielectric film formed over the first dielectric film; and a gate electrode formed over the gate insulating film and including a polycrystalline silicon film, whereby the local abnormal growth of the polycrystalline silicon film in the process of forming the polycrystalline silicon film is prevented, and the gate leakage current can be much decreased.Type: GrantFiled: February 2, 2004Date of Patent: September 20, 2005Assignee: Fujitsu LimitedInventors: Chikako Yoshida, Hiroshi Minakata, Masaomi Yamaguchi, Shinji Miyagaki, Yasuyuki Tamura
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Publication number: 20050142715Abstract: A semiconductor device has: a silicon substrate; a silicon oxide layer formed on the surface of the silicon substrate; a high dielectric constant insulating film including a first oxide layer formed above the silicon oxide layer and made of a high dielectric constant film having a dielectric constant higher than silicon oxide and a first nitride layer formed above the first oxide layer and made of nitride having an oxygen intercepting capability, or a high dielectric constant insulating film including a first oxide film formed on the silicon oxide layer, a second oxide layer formed on the first oxide layer and a third oxide layer formed on the second oxide layer, the first and third oxide layers having an oxygen diffusion coefficient smaller than the second oxide layer; and a gate electrode formed on the high dielectric constant insulating layer and made of oxidizable material.Type: ApplicationFiled: October 27, 2004Publication date: June 30, 2005Applicant: FUJITSU LIMITEDInventors: Tsunehisa Sakoda, Yoshihiro Sugiyama, Masaomi Yamaguchi, Hiroshi Minakata
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Patent number: 6835976Abstract: A method of manufacturing a semiconductor device has the steps of: (a) forming a lower electrode made of rare metal above a semiconductor substrate; (b) depositing a capacitor dielectric film made of a high dielectric material or ferroelectric oxide on the lower electrode; (c) forming a laminated layer on the capacitor dielectric film, the laminated layer including an upper electrode layer made of rare metal and an adhesive layer with or without an SiO2 mask layer thoreon; (d) patterning the laminated layer; (e) chemically processing the patterned, laminated layer to remove a surface layer of the laminated layer; and (f) forming an interlayer insulating film over the semiconductor substrate, covering the chemically processed, laminated layer. An adhesion force between the rare metal layer and insulating layer can be increased.Type: GrantFiled: June 10, 2003Date of Patent: December 28, 2004Assignee: Fujitsu LimitedInventors: Jun Lin, Hiroshi Minakata, Akihiro Shimada, Toshiya Suzuki, Daisuke Matsunaga
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Publication number: 20040238841Abstract: The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1-xOy (0.7<x<1) formed over a semiconductor substrate, and a second dielectric film different from the first dielectric film formed over the first dielectric film; and a gate electrode formed over the gate insulating film and including a polycrystalline silicon film, whereby the local abnormal growth of the polycrystalline silicon film in the process of forming the polycrystalline silicon film is prevented, and the gate leakage current can be much decreased.Type: ApplicationFiled: February 2, 2004Publication date: December 2, 2004Applicant: Fujitsu LimitedInventors: Chikako Yoshida, Hiroshi Minakata, Masaomi Yamaguchi, Shinji Miyagaki, Yasuyuki Tamura