Patents by Inventor Hiroshi Mine

Hiroshi Mine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220344935
    Abstract: It is provided a management system for managing renewable energy verification comprising: an arithmetic device configured to execute predetermined processing; a storage device coupled to the arithmetic device, an input unit configured to receive a supply ratio of renewable energy in a manufacturing process, and input quantities of a renewable energy-derived raw material and a renewable energy-derived part out of raw materials and parts input to the manufacturing process; and an RE verification granting module configured to calculate, with use of the received input about the supply ratio of renewable energy and about the input quantities of the renewable energy-derived raw material and the renewable energy-derived part, at least one of the number of pieces to be granted renewable energy verification out of pieces of a manufactured item manufactured by the manufacturing process, or a ratio of pieces of the manufactured item that are to be granted renewable energy verification.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 27, 2022
    Inventors: Michiki NAKANO, Hiroshi MINE
  • Patent number: 11192562
    Abstract: A device to be controlled used for an operation of a vehicle, a determination device used for controlling the device, and a control information management device different from the determination device are included.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: December 7, 2021
    Assignee: HITACHI, LTD.
    Inventors: Takuro Mori, Mitsuhiro Kitani, Hiroshi Mine
  • Patent number: 11048493
    Abstract: Provided is a computer system which, by transmitting software to a terminal for updating a control system of the terminal, enables the terminal to properly function based on the software. A computer system configured so as to be able to remotely update software of a terminal, wherein a processor generates an update file for updating the software of the terminal and stores the generated update file in a memory, identifies a specific terminal to which the update file should be transmitted, reads the update file from the memory and transmits the update file from a transmission module to the specific terminal, receives operational information of the update file from the specific terminal via a reception module, and determines whether it is necessary to distribute the update file to a terminal other than the specific terminal based on the operational information.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: June 29, 2021
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Soki Sakurai, Noboru Kiyama, Atsushi Katou
  • Publication number: 20210026970
    Abstract: The present invention provides a security evaluation server including: a hierarchy generation unit configured to generate information regarding a plurality of system hierarchies in an evaluation subject system; an evaluation unit configured to, based on the information regarding the plurality of system hierarchies generated by the hierarchy generation unit, calculate an evaluation value of protection effectiveness based on a security function requirement included in each of the plurality of system hierarchies in the evaluation subject system, and calculate an evaluation value of protection effectiveness based on a combination of the security function requirements; and a verification unit configured to verify whether each of the security function requirements in the evaluation subject system is in excess or insufficient, based on each of the evaluation values calculated by the evaluation unit and a target value.
    Type: Application
    Filed: December 13, 2018
    Publication date: January 28, 2021
    Applicant: HITACHI, LTD.
    Inventors: Yiwen CHEN, Satoshi KAI, Eriko ANDO, Hiroshi MINE, Satoshi IIMURO, Takamasa KAWAGUCHI
  • Publication number: 20200023857
    Abstract: A device to be controlled used for an operation of a vehicle, a determination device used for controlling the device, and a control information management device different from the determination device are included.
    Type: Application
    Filed: May 23, 2018
    Publication date: January 23, 2020
    Inventors: Takuro MORI, Mitsuhiro KITANI, Hiroshi MINE
  • Patent number: 10310840
    Abstract: Provided is a computer system capable of managing the performance of processing upon transmitting software to terminals. The present invention is a computer system comprising a plurality of modules which sequentially execute processing up to transmitting the software to the terminal, a controller which collects an operation log of each of the plurality of modules, and a memory which stores the operation logs collected by the controller, wherein the controller generates an operating performance of a prescribed module among the plurality of modules based on the operation logs stored in the memory.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: June 4, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Soki Sakurai, Atsushi Katou, Noboru Kiyama, Hiroshi Mine
  • Publication number: 20180095745
    Abstract: Provided is a computer system which, by transmitting software to a terminal for updating a control system of the terminal, enables the terminal to properly function based on the software. A computer system configured so as to be able to remotely update software of a terminal, wherein a processor generates an update file for updating the software of the terminal and stores the generated update file in a memory, identifies a specific terminal to which the update file should be transmitted, reads the update file from the memory and transmits the update file from a transmission module to the specific terminal, receives operational information of the update file from the specific terminal via a reception module, and determines whether it is necessary to distribute the update file to a terminal other than the specific terminal based on the operational information.
    Type: Application
    Filed: August 3, 2017
    Publication date: April 5, 2018
    Inventors: Hiroshi MINE, Soki SAKURAI, Noboru KIYAMA, Atsushi KATOU
  • Publication number: 20180095744
    Abstract: Provided is a computer system capable of managing the performance of processing upon transmitting software to terminals. The present invention is a computer system comprising a plurality of modules which sequentially execute processing up to transmitting the software to the terminal, a controller which collects an operation log of each of the plurality of modules, and a memory which stores the operation logs collected by the controller, wherein the controller generates an operating performance of a prescribed module among the plurality of modules based on the operation logs stored in the memory.
    Type: Application
    Filed: August 2, 2017
    Publication date: April 5, 2018
    Inventors: Soki SAKURAI, Atsushi KATOU, Noboru KIYAMA, Hiroshi MINE
  • Publication number: 20180004246
    Abstract: A problem to be solved by the present invention is, in a computer system, to reduce processing delay from wait times which occur in timer access. According to the present invention, using either a CPU core (hereinafter “processing core”) other than a CPU core which executes an application, or a DMA device, a latest timer value is always transferred from a timer device to a primary storage device. The processing core reads the transferred value upon the primary storage device instead of accessing a register of the timer device, thereby avoiding a wait which occurs when directly reading the timer value of the timer device. The transfer of the value is carried out asynchronously from the processing of the processing core, thus obviating the need for the processing core to wait for the completion of the transfer. Accordingly, it is also unnecessary for the processing core to process an interrupt or a notification from another CPU core or the DMA device.
    Type: Application
    Filed: January 23, 2015
    Publication date: January 4, 2018
    Inventors: Taku SHIMOSAWA, Hidehiro KAWAI, Hiroshi MINE, Satoshi OOSHIMA
  • Patent number: 9841993
    Abstract: A problem with conventional art is that, in an environment wherein a plurality of interrupts having different priorities for processing occur in an overlapping manner from external devices, responding to high-priority interrupts while ensuring execution intervals of periodic tasks has been difficult. A partition execution control device according to the present invention comprises: a first management table which stores, for each partition, initial time slices, remaining time slices, execution priorities, execution states, and an interrupt disable level for suppressing the interrupts from the external devices; and a second management table which stores the interrupt priorities of the external devices and partitions to which the interrupts are to be output.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: December 12, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Satoshi Oshima
  • Publication number: 20160370770
    Abstract: To automate confirmation of a control program. An engineering tool includes a data separating unit that separates data about an object registered in a control program from real data in a control device; a state changing unit that changes the state of the object, which is a detection source, in the control device after the separation of the data; a state acquiring unit that acquires the state of the object, which is a change destination, from the control device after the change of the state; a history acquiring unit that acquires history data concerning the control program from a monitoring device; and a confirming unit that compares results of the acquisition by the state acquiring unit and the history acquiring unit with a result of an arithmetic operation in a normal time of the control program to confirm the operation of the control program.
    Type: Application
    Filed: June 17, 2016
    Publication date: December 22, 2016
    Applicant: AZBIL CORPORATION
    Inventor: Hiroshi MINE
  • Publication number: 20160328261
    Abstract: A problem with conventional art is that, in an environment wherein a plurality of interrupts having different priorities for processing occur in an overlapping manner from external devices, responding to high-priority interrupts while ensuring execution intervals of periodic tasks has been difficult. A partition execution control device according to the present invention comprises: a first management table which stores, for each partition, initial time slices, remaining time slices, execution priorities, execution states, and an interrupt disable level for suppressing the interrupts from the external devices; and a second management table which stores the interrupt priorities of the external devices and partitions to which the interrupts are to be output.
    Type: Application
    Filed: December 27, 2013
    Publication date: November 10, 2016
    Inventors: Hiroshi MINE, Satoshi OSHIMA
  • Patent number: 8612715
    Abstract: A storage system 1000 providing a storage area to an external device 1500 comprises a plurality of storage apparatuses 1100, 1200 and 1300 of different performance capabilities, and a storage controller 2600. The storage controller 2600 holds storage cost coefficients 3202 of the respective storage apparatuses 1100, 1200 and 1300, user cost allocation information 3302 for each user using the storage system 1000 from the external device 1500, and user cost distribution information 3402 that defines, for each user, proportions of an available space amount distributed to the storage apparatuses 1100, 1200 and 1300. The storage controller 2600 calculates an ideal utilization 3502 for each user, from the storage cost coefficients 3202 and the user cost distribution information 3402, and allocates, for each user, the ideal utilization 3502 to each of the storage apparatuses 1100, 1200 and 1300, in the order of the performance capabilities from highest to lowest.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 17, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Hitoshi Kamei, Takahiro Nakano
  • Patent number: 8504780
    Abstract: A computer includes first and second processors, first and second I/O devices, a shared memory, and an interrupt controller. The first processor issues a control command for causing the first I/O device to read target data from the first apparatus and store the target data in the shared memory. The first I/O device reads the target data from the first apparatus and, transfers the target data to the shared memory, and generates an I/O complete interrupt. The interrupt controller delivers the generated I/O complete interrupt to the second processor. When the second processor receives the I/O complete interrupt, the second processor issues a control command for causing the second I/O device to read the target data from the shared memory and send the target data to the second apparatus. The second I/O device reads the target data from the shared memory and sends the target data to the second apparatus.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: August 6, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Ken Nomura, Damien Le Moal, Tadashi Takeuchi
  • Patent number: 8499112
    Abstract: An aspect of the invention is a storage control apparatus, comprising a plurality of processors, a memory, an I/O device coupled to a storage device, a virtualization module that allocates a first processor to a first guest and a second processor to a second guest from among the plurality of processors, and an interrupt control module that receives an interrupt from the I/O device and transmits the interrupt to any one of the plurality of processors, wherein the virtualization module comprises, a state detection module that detects at least one of a state of the first guest and a state of the first processor, and an interrupt delivery destination control module that switches the interrupt with respect to the first processor to the second processor when at least one of the state of the first guest and the state of the first processor becomes a predetermined state.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: July 30, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Ken Nomura, Damien Le Moal, Tadashi Takeuchi, Masaaki Iwasaki
  • Patent number: 8413197
    Abstract: In this video delivery device including: a storage device storing key frame information including a key frame number included in a contents file and offset from the beginning of a file; and a delivery control unit, which executes delivery in a predetermined cycle, the delivery control unit refers to the key frame information cycle by cycle in executing the trick play, and transmits the key frame having the offset closest to the delivery time among the key frames included in the contents file.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: April 2, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Shinji Kimura, Kaoru Konishi, Tomokazu Ikki, Naohisa Seko
  • Publication number: 20130046911
    Abstract: An aspect of the invention is a storage control apparatus, comprising a plurality of processors, a memory, an I/O device coupled to a storage device, a virtualization module that allocates a first processor to a first guest and a second processor to a second guest from among the plurality of processors, and an interrupt control module that receives an interrupt from the I/O device and transmits the interrupt to any one of the plurality of processors, wherein the virtualization module comprises, a state detection module that detects at least one of a state of the first guest and a state of the first processor, and an interrupt delivery destination control module that switches the interrupt with respect to the first processor to the second processor when at least one of the state of the first guest and the state of the first processor becomes a predetermined state.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 21, 2013
    Applicant: HITACHI, LTD.
    Inventors: Hiroshi Mine, Ken Nomura, Damien Le Moal, Tadashi Takeuchi, Masaaki Iwasaki
  • Publication number: 20120265961
    Abstract: A storage system 1000 providing a storage area to an external device 1500 comprises a plurality of storage apparatuses 1100, 1200 and 1300 of different performance capabilities, and a storage controller 2600. The storage controller 2600 holds storage cost coefficients 3202 of the respective storage apparatuses 1100, 1200 and 1300, user cost allocation information 3302 for each user using the storage system 1000 from the external device 1500, and user cost distribution information 3402 that defines, for each user, proportions of an available space amount distributed to the storage apparatuses 1100, 1200 and 1300. The storage controller 2600 calculates an ideal utilization 3502 for each user, from the storage cost coefficients 3202 and the user cost distribution information 3402, and allocates, for each user, the ideal utilization 3502 to each of the storage apparatuses 1100, 1200 and 1300, in the order of the performance capabilities from highest to lowest.
    Type: Application
    Filed: June 21, 2012
    Publication date: October 18, 2012
    Inventors: HIROSHI MINE, Hitoshi Kamei, Takahiro Nakano
  • Publication number: 20120260017
    Abstract: A computer includes first and second processors, first and second I/O devices, a shared memory, and an interrupt controller. The first processor issues a control command for causing the first I/O device to read target data from the first apparatus and store the target data in the shared memory. The first I/O device reads the target data from the first apparatus and, transfers the target data to the shared memory, and generates an I/O complete interrupt. The interrupt controller delivers the generated I/O complete interrupt to the second processor. When the second processor receives the I/O complete interrupt, the second processor issues a control command for causing the second I/O device to read the target data from the shared memory and send the target data to the second apparatus. The second I/O device reads the target data from the shared memory and sends the target data to the second apparatus.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 11, 2012
    Applicant: HITACHI, LTD.
    Inventors: Hiroshi Mine, Ken Nomura, Damien Le Moal, Tadashi Takeuchi
  • Patent number: 8260947
    Abstract: A media delivery apparatus for relaying media data streaming-delivered from a server to a client terminal through a network, including a receiving portion for receiving packets transmitted from the server to the network when stream-delivering the media data, and a storage device, wherein: each of the packets contains at least one media data element as a split of the media data and is constructed according to a certain protocol; and the receiving portion extracts the media data element, generates information necessary for reconstructing a packet having the same construction as that of the packet containing the media data and stores the necessary information in addition to the extracted media data in the storage device.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: September 4, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Tadashi Takeuchi, Ken Nomura