Patents by Inventor Hiroshi Miyata
Hiroshi Miyata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869961Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.Type: GrantFiled: January 19, 2022Date of Patent: January 9, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hiroshi Miyata, Seiji Noguchi, Souichi Yoshida, Hiromitsu Tanabe, Kenji Kouno, Yasushi Okura
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Publication number: 20220140121Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.Type: ApplicationFiled: January 19, 2022Publication date: May 5, 2022Applicants: FUJI ELECTRIC CO., LTD., DENSO CORPORATIONInventors: Hiroshi MIYATA, Seiji NOGUCHI, Souichi YOSHIDA, Hiromitsu TANABE, Kenji KOUNO, Yasushi OKURA
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Patent number: 11264490Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.Type: GrantFiled: November 29, 2018Date of Patent: March 1, 2022Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATIONInventors: Hiroshi Miyata, Seiji Noguchi, Souichi Yoshida, Hiromitsu Tanabe, Kenji Kouno, Yasushi Okura
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Publication number: 20210384331Abstract: A semiconductor device including: a semiconductor substrate; a temperature sensing unit provided on a front surface of the semiconductor substrate; an anode pad and a cathode pad electrically connected with the temperature sensing unit; a front surface electrode being set to a predetermined reference potential; and a bidirectional diode unit electrically connected in a serial bidirectional way between the cathode pad and the front surface electrode is provided. The bidirectional diode unit may be arranged between the anode pad and the cathode pad on the front surface.Type: ApplicationFiled: August 24, 2021Publication date: December 9, 2021Inventors: Shigeki SATO, Ryu ARAKI, Hiroshi MIYATA, Soichi YOSHIDA
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Publication number: 20210384333Abstract: A semiconductor device including: a semiconductor substrate; a temperature sensing unit provided on a front surface of the semiconductor substrate; an anode pad and a cathode pad electrically connected with the temperature sensing unit; a front surface electrode being set to a predetermined reference potential; and a bidirectional diode unit electrically connected in a serial bidirectional way between the cathode pad and the front surface electrode is provided. The output comparison diode unit may be arranged between the anode pad and the cathode pad. The temperature sensing unit may include a temperature sensing diode, and the output comparison diode unit may include a diode connected in inverse parallel to the temperature sensing diode.Type: ApplicationFiled: August 24, 2021Publication date: December 9, 2021Inventors: Shigeki SATO, Toshiyuki MATSUI, Ryu ARAKI, Hiroshi MIYATA, Soichi YOSHIDA
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Publication number: 20210376132Abstract: A semiconductor device includes a plurality of first trenches each having a stripe-shape, extending in parallel to each other, a first mesa region, a second mesa region, a first interlayer insulating film covering the first mesa region and the second mesa region, and a first contact hole penetrating the first interlayer insulating film to the first mesa region, and extending along a longitudinal direction of the first trenches. The first mesa region includes emitter regions of a first conductivity type periodically provided along the longitudinal direction of the first trenches in a plan view, contact regions of a second conductivity type provided such that each of the emitter regions is interposed between the contact regions along the longitudinal direction in the plan view, and a base region of the second conductivity type provided immediately below the emitter regions and the contact regions.Type: ApplicationFiled: August 16, 2021Publication date: December 2, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hitoshi ABE, Hiroshi MIYATA, Hidenori TAKAHASHI, Seiji NOGUCHI, Naoya SHIMADA
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Patent number: 11127844Abstract: A semiconductor device includes: a drift layer; a mesa region that is interposed between adjacent trenches on the drift layer; a gate electrode buried in each trench through a gate insulating film; a base region of buried in the mesa region; a plurality of emitter regions that are periodically buried in a surface layer portion of the base region along a longer direction of the trench; and contact regions that are alternately buried in the longer direction together with the emitter regions such that each emitter region is interposed between the contact regions, are deeper than the emitter region, and extend immediately below the emitter region so as to be separated from each other, a contact-region contact-width in the longer direction defined in a surface of the contact region being less than an emitter-region contact-width in the longer direction defined in a surface of the emitter region.Type: GrantFiled: January 26, 2017Date of Patent: September 21, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hitoshi Abe, Hiroshi Miyata, Hidenori Takahashi, Seiji Noguchi, Naoya Shimada
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Patent number: 10770456Abstract: A semiconductor device including a semiconductor substrate is provided. The semiconductor substrate includes a transistor region, and the transistor region includes a drift region, a plurality of trench portions, a plurality of emitter regions and a plurality of contact regions, and an accumulation region provided between the drift region and the plurality of emitter regions in a depth direction, and having a higher first-conductivity-type doping concentration than the drift region. A first outermost contact region is an outermost one of the plurality of contact regions in a direction parallel to the first direction, and a length of the first outermost contact region in the first direction is longer than a length in the first direction of one contact region of the plurality of contact regions other than the first outermost contact region, and the accumulation region terminates at a position below the first outermost contact region.Type: GrantFiled: January 25, 2019Date of Patent: September 8, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Soichi Yoshida, Hiroshi Miyata
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Publication number: 20200049682Abstract: An object of the present invention is to increase the accuracy of water quality measurement of ballast waters with different oxidant concentrations. A ballast water measurement apparatus (2 or 62) is provided with: a first measuring unit (6-1 or 64-1) for measuring an oxidant concentration of ballast water after addition of an oxidant or ballast water before addition of a neutralizing agent; a second measuring unit (6-2 or 64-2) for measuring an oxidant concentration of ballast water after neutralization of the oxidant; and a casing (4) that accommodates the first measuring unit and the second measuring unit. Oxidant concentration measurement ranges of the first measuring unit and the second measuring unit are different.Type: ApplicationFiled: September 15, 2017Publication date: February 13, 2020Applicant: KURITA WATER INDUSTRIES LTD.Inventors: Kotaro FUKUZAWA, Hiroshi MIYATA
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Publication number: 20190157264Abstract: A semiconductor device including a semiconductor substrate is provided. The semiconductor substrate includes a transistor region, and the transistor region includes a drift region, a plurality of trench portions, a plurality of emitter regions and a plurality of contact regions, and an accumulation region provided between the drift region and the plurality of emitter regions in a depth direction, and having a higher first-conductivity-type doping concentration than the drift region. A first outermost contact region is an outermost one of the plurality of contact regions in a direction parallel to the first direction, and a length of the first outermost contact region in the first direction is longer than a length in the first direction of one contact region of the plurality of contact regions other than the first outermost contact region, and the accumulation region terminates at a position below the first outermost contact region.Type: ApplicationFiled: January 25, 2019Publication date: May 23, 2019Inventors: Soichi YOSHIDA, Hiroshi MIYATA
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Publication number: 20190097030Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.Type: ApplicationFiled: November 29, 2018Publication date: March 28, 2019Applicants: FUJI ELECTRIC CO., LTD., DENSO CORPORATIONInventors: Hiroshi Miyata, Seiji Noguchi, Souichi Yoshida, Hiromitsu Tanabe, Kenji Kouno, Yasushi Okura
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Patent number: 10104014Abstract: A data transferring system includes a switch and a controller. The switch transfers data from a transmission source to a transmission destination with reference to a table in which a first information and a second information are associated. The controller includes a setter configured to set a tentative table to the switch, the tentative table storing the second information for outputting data, which is matched with the condition represented by the first information, to the controller, an obtainer configured to obtain a route information representing a route between the transmission source and the transmission destination, and an updater configured to update the tentative table to a table in which an outputting destination of data, which is matched with the condition represented by the first information, is changed in accordance with the route information.Type: GrantFiled: July 31, 2015Date of Patent: October 16, 2018Assignee: Yokogawa Electric CorporationInventors: Senji Watanabe, Hiroshi Miyata
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Patent number: 9911733Abstract: A semiconductor device, including a semiconductor substrate, a plurality of trenches formed on a front surface of the semiconductor substrate, a plurality of gate electrodes formed in the trenches, a base region and an anode region formed between adjacent trenches respectively in first and second element regions of the semiconductor substrate, a plurality of emitter regions and contact regions selectively formed in the base region, an interlayer insulating film covering the gate electrodes, first and second contact holes penetrating the interlayer insulating film, a plurality of contact plugs embedded in the first contact holes, a first electrode contacting the contact plugs and contacting the anode region via the second contact hole, a collector region and a cathode region formed on a back surface of the semiconductor substrate respectively in the first and second element regions, and a second electrode contacting the collector region and the cathode region.Type: GrantFiled: October 28, 2016Date of Patent: March 6, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Souichi Yoshida, Hiroshi Miyata
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Publication number: 20170141216Abstract: A semiconductor device includes: a drift layer; a mesa region that is interposed between adjacent trenches on the drift layer; a gate electrode buried in each trench through a gate insulating film; a base region of buried in the mesa region; a plurality of emitter regions that are periodically buried in a surface layer portion of the base region along a longer direction of the trench; and contact regions that are alternately buried in the longer direction together with the emitter regions such that each emitter region is interposed between the contact regions, are deeper than the emitter region, and extend immediately below the emitter region so as to be separated from each other, a contact-region contact-width in the longer direction defined in a surface of the contact region being less than an emitter-region contact-width in the longer direction defined in a surface of the emitter region.Type: ApplicationFiled: January 26, 2017Publication date: May 18, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hitoshi ABE, Hiroshi MIYATA, Hidenori TAKAHASHI, Seiji NOGUCHI, Naoya SHIMADA
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Patent number: 9642004Abstract: The present invention provides an access point device and system for a wireless local area network, and related methods thereof. On the access point device, a same ESS is divided into a plurality of VLANs, wherein the access point device comprises a broadcast key management module which is used for managing broadcast keys encrypting broadcast information and a broadcast key storage device which is used for storing the broadcast keys. The broadcast keys are stored in the broadcast key storage device in a way of corresponding to VLAN IDs of the VLANs, and the broadcast key management module can obtain the corresponding broadcast keys through the VLAN IDs.Type: GrantFiled: June 18, 2012Date of Patent: May 2, 2017Assignee: Yokogawa Electric CorporationInventors: Yue Wang, Hao Li, Dong Wang, Hiroshi Miyata
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Publication number: 20170047322Abstract: A semiconductor device, including a semiconductor substrate, a plurality of trenches formed on a front surface of the semiconductor substrate, a plurality of gate electrodes formed in the trenches, a base region and an anode region formed between adjacent trenches respectively in first and second element regions of the semiconductor substrate, a plurality of emitter regions and contact regions selectively formed in the base region, an interlayer insulating film covering the gate electrodes, first and second contact holes penetrating the interlayer insulating film, a plurality of contact plugs embedded in the first contact holes, a first electrode contacting the contact plugs and contacting the anode region via the second contact hole, a collector region and a cathode region formed on a back surface of the semiconductor substrate respectively in the first and second element regions, and a second electrode contacting the collector region and the cathode region.Type: ApplicationFiled: October 28, 2016Publication date: February 16, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Souichi YOSHIDA, Hiroshi MIYATA
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Patent number: 9397994Abstract: A packet forwarding device includes: an evaluation unit configured to judge whether or not authentication information is stored in a header, the authentication information being for authenticating communication quality control information stored in the header of a packet transmitted via a network, and evaluate whether or not the authentication information is proper, the evaluation being made when the authentication information is stored in the header; and a forwarding unit that configured to control a communication quality using the communication quality control information, and forward the packet toward a transmission destination, the control being made when the authentication information is evaluated by the evaluation unit to be proper.Type: GrantFiled: July 24, 2013Date of Patent: July 19, 2016Assignee: YOKOGAWA ELECTRIC CORPORATIONInventor: Hiroshi Miyata
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Publication number: 20160065501Abstract: A data transferring system includes a switch and a controller. The switch transfers data from a transmission source to a transmission destination with reference to a table in which a first information and a second information are associated. The controller includes a setter configured to set a tentative table to the switch, the tentative table storing the second information for outputting data, which is matched with the condition represented by the first information, to the controller, an obtainer configured to obtain a route information representing a route between the transmission source and the transmission destination, and an updater configured to update the tentative table to a table in which an outputting destination of data, which is matched with the condition represented by the first information, is changed in accordance with the route information.Type: ApplicationFiled: July 31, 2015Publication date: March 3, 2016Applicant: YOKOGAWA ELECTRIC CORPORATIONInventors: Senji WATANABE, Hiroshi MIYATA
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Publication number: 20150195267Abstract: A packet forwarding device includes: an evaluation unit configured to judge whether or not authentication information is stored in a header, the authentication information being for authenticating communication quality control information stored in the header of a packet transmitted via a network, and evaluate whether or not the authentication information is proper, the evaluation being made when the authentication information is stored in the header; and a forwarding unit that configured to control a communication quality using the communication quality control information, and forward the packet toward a transmission destination, the control being made when the authentication information is evaluated by the evaluation unit to be proper.Type: ApplicationFiled: July 24, 2013Publication date: July 9, 2015Applicant: YOKOGAWA ELECTRIC CORPORATIONInventor: Hiroshi Miyata
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Patent number: 9006579Abstract: A method of manufacturing a printed circuit board includes: forming a copper layer of an interconnection pattern on a base film; laminating a cover lay on the base film so as to expose a part of the copper layer from the cover lay and cover the copper layer by the cover lay; mechanically polishing at least the exposed portion of the copper layer; and performing a plating process on the exposed portion of the copper layer so as to form a plated layer on the copper layer, and the angles ?1 and ?2 between the polishing direction of the exposed portion of the copper layer and the bending lines C1 and C2 satisfy the following formula (1): 30°??1 and ?2?150°??(1).Type: GrantFiled: September 14, 2012Date of Patent: April 14, 2015Assignee: Fujikura Ltd.Inventors: Masatoshi Inaba, Hiroshi Miyata, Hirohito Watanabe