Abstract: A gas determination method uses a sensor having a field-effect transistor structure including a gate electrode, an insulating film formed on the gate electrode, a source electrode and a drain electrode formed on the insulating film, and a graphene layer formed on the insulating film and connecting the source electrode and the drain electrode to each other. The gas determination method includes: supplying gas to the graphene layer; applying a first voltage to the gate electrode for a predetermined period of time; and thereafter measuring a change in a current flowing between the source electrode and the drain electrode when a sweep voltage is applied to the gate electrode, repeating the same current measurement with a second voltage different from the first voltage, and determining the gas based on the measurement results.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A transistor device comprising source and drain regions (S, D), a nanotube structure (2, 3) providing a path for electrical charge carriers between the source and drain regions, and a gate region (4). The nanotube structure has its conduction band structure locally modified in the gate region, e.g. by doping, for controlling the passage of the charge carriers in the path. The device can be used as a flash memory or as a memory element in a DRAM.

Abstract: A magnetoelectric device responsive to an applied magnetic field, e.g. for use as a reading head for data stored in magnetic storage media, comprises first and second ferromagnetic regions (3, 4) with a channel region (5) between them, the ferromagnetic regions being configured so that charge carriers with a particular spin polarization which can pass through the first region, pass through the second region as a function of the relative orientations of magnetization of the ferromagnetic regions produced by the applied magnetic field such that the device exhibits a conductivity as a function of the strength of the applied field. The channel region (5) includes a nanotube (6) which may be formed of carbon, configured to provide a quasi-one-dimensional channel to cause charge carriers which pass through the first ferromagnetic region to maintain their spin polarization as they pass towards the second ferromagnetic region. In an alternative embodiment a deposited carbon layer (14) is used in the channel region.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only-Memory) cannot be configured as a high speed/large capacity memory.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

Abstract: A semiconductor logic element is provided which is capable of a plurality of logic operations. The semiconductor logic element includes a semiconductor substrate on which is disposed at least three control electrodes and an output electrode for outputting signals in response to inputs to said control electrodes, making it possible to significantly reduce the number of elements constituting a logic circuit and to provide high speed processors and electronic computers. Logic circuitry and apparatus using the semiconductor logic elements are also provided.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si.sub.3 N.sub.4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

Abstract: A semiconductor device is disclosed, which includes a multiple negative differential resistance element having negative differential resistance characteristics at at least two places in the current-voltage characteristics, and which is suitable for constructing a neural network having a high density integration and a high reliability.

Abstract: A resonant tunneling device includes a superlattice layer which includes an interlaminated structure of three semiconductor layers each having a narrow energy bandgap and serving as a quantum well layer and four semiconductor layers each having a wide energy bandgap and serving as a barrier layer and in which three quantum levels are formed in the quantum well layers. A resonant tunneling phenomenon produced between the quantum levels provides peak current values which are substantially equal to each other, peak voltages which can be set independently from each other, and peak-to-valley (P/V) ratios which are high, thereby realizing a resonant tunneling device which has an excellent performance as a three state logic element for a logic circuit. By increasing the number of quantum well layers and the number of barrier layers, a logic element of four or more states can be realized for a logic circuit.