Patents by Inventor Hiroshi Momiji

Hiroshi Momiji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8034715
    Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: October 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
  • Publication number: 20090263943
    Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
    Type: Application
    Filed: June 26, 2009
    Publication date: October 22, 2009
    Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
  • Patent number: 7569457
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: August 4, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Patent number: 7553766
    Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: June 30, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
  • Publication number: 20080132022
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Application
    Filed: November 9, 2007
    Publication date: June 5, 2008
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Publication number: 20080090358
    Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
    Type: Application
    Filed: December 4, 2007
    Publication date: April 17, 2008
    Inventors: Shinji NISHIHARA, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
  • Patent number: 7314830
    Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: January 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
  • Patent number: 7314805
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: January 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Publication number: 20070184603
    Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
    Type: Application
    Filed: April 6, 2007
    Publication date: August 9, 2007
    Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
  • Patent number: 7214577
    Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: May 8, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
  • Publication number: 20070004163
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Application
    Filed: September 13, 2006
    Publication date: January 4, 2007
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Patent number: 7118983
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: October 10, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Patent number: 7094655
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 22, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Patent number: 7094642
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: August 22, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Patent number: 7074665
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: July 11, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Patent number: 7064040
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and’ a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: June 20, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Publication number: 20050250268
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 10, 2005
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Publication number: 20050250269
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 10, 2005
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Publication number: 20050239258
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Application
    Filed: June 30, 2005
    Publication date: October 27, 2005
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Publication number: 20050186729
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Application
    Filed: April 21, 2005
    Publication date: August 25, 2005
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki