Patents by Inventor Hiroshi Momiji
Hiroshi Momiji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8034715Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.Type: GrantFiled: June 26, 2009Date of Patent: October 11, 2011Assignee: Renesas Electronics CorporationInventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
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Publication number: 20090263943Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.Type: ApplicationFiled: June 26, 2009Publication date: October 22, 2009Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
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Patent number: 7569457Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: GrantFiled: November 9, 2007Date of Patent: August 4, 2009Assignee: Renesas Technology Corp.Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Patent number: 7553766Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.Type: GrantFiled: December 4, 2007Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
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Publication number: 20080132022Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: ApplicationFiled: November 9, 2007Publication date: June 5, 2008Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Publication number: 20080090358Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.Type: ApplicationFiled: December 4, 2007Publication date: April 17, 2008Inventors: Shinji NISHIHARA, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
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Patent number: 7314830Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.Type: GrantFiled: April 6, 2007Date of Patent: January 1, 2008Assignee: Renesas Technology Corp.Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
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Patent number: 7314805Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: GrantFiled: September 13, 2006Date of Patent: January 1, 2008Assignee: Renesas Technology Corp.Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Publication number: 20070184603Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.Type: ApplicationFiled: April 6, 2007Publication date: August 9, 2007Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
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Patent number: 7214577Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.Type: GrantFiled: December 8, 2004Date of Patent: May 8, 2007Assignee: Renesas Technology Corp.Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
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Publication number: 20070004163Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: ApplicationFiled: September 13, 2006Publication date: January 4, 2007Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Patent number: 7118983Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: GrantFiled: June 30, 2005Date of Patent: October 10, 2006Assignee: Renesas Technology Corp.Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Patent number: 7094655Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: GrantFiled: June 30, 2005Date of Patent: August 22, 2006Assignee: Renesas Technology Corp.Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Patent number: 7094642Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: GrantFiled: April 21, 2005Date of Patent: August 22, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Patent number: 7074665Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: GrantFiled: November 6, 2003Date of Patent: July 11, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Patent number: 7064040Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and’ a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: GrantFiled: June 30, 2005Date of Patent: June 20, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Publication number: 20050250268Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: ApplicationFiled: June 30, 2005Publication date: November 10, 2005Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Publication number: 20050250269Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: ApplicationFiled: June 30, 2005Publication date: November 10, 2005Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Publication number: 20050239258Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: ApplicationFiled: June 30, 2005Publication date: October 27, 2005Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
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Publication number: 20050186729Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: ApplicationFiled: April 21, 2005Publication date: August 25, 2005Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki