Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a source drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

Abstract: A semiconductor device of this invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is hetero-bipolar transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

Abstract: A semiconductor device of the present invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is heterojunction transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

Abstract: A contact hole for guiding an emitter electrode of bipolar transistors continuously arrayed and a contact hole for guiding a base electrode are positioned not to be arranged in the continuous array direction of the bipolar transistors. Also, the emitter electrode and the base electrode are respectively drawn from these contact holes in two directions different from the continuous array direction of the bipolar transistors. At least one of the base electrode and the emitter electrode is formed on a conductive layer of a polycide structure contacting an active region in a substrate to be connected.

Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a gate and/or drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

Abstract: A BiMOS integrated circuit device comprises a bipolar transistor and at least one MOSFET. The collector and emitter of the bipolar transistor are connected to a high potential source and a low potential source, respectively. The MOSFET has two gate electrodes, a source, and a drain. The source is connected to the high potential source, and the drain is the base of the bipolar transistor by a diffusion layer. The diffusion layer is located between the gate electrodes, and serves as both the base of the bipolar transistor and the drain of the MOSFET. Therefore, the MOSFET has a great channel width, and a large current can be supplied to the base of the bipolar transistor. In other words, the MOSFET has a great driving capability, and the bipolar transistor has a high amplification factor.

Abstract: Disclosed here in is a semiconductor integrated circuit comprising a substrate, a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of word lines, and a plurality of bit lines, and a plurality of word-line drive circuits located near the memory cell array. Each of the word-line drive circuits is a Bi-NMOS circuit which comprises a bipolar transistor for pulling up the potential of the word line and an N-channel MOS transistor for pulling down the potential of the word line. The collector layers of the bipolar transistors are formed of one and the same layer.

Abstract: At least part of a low impurity concentration collector region which lies between the emitter and collector regions of a bipolar transistor in a Bi-CMOS device is formed to have a low impurity concentration. Therefore, a high emitter-collector withstanding voltage can be obtained. Further, at least part of the low impurity concentration collector region which lies between the base region and an opposite conductivity type region is formed to have a high impurity concentration. Therefore, the punch-through withstanding voltage of a parasitic transistor formed of the base, collector and, opposite conductivity type region can be enhanced, and, at the same time, the collector resistance can be reduced.

Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a gate and/or drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

Abstract: A semiconductor device includes a semiconductor substrate, a bipolar transistor and a MOS transistor. The bipolar transistor is formed on the semiconductor substrate and has electrodes. A base electrode of the bipolar transistor and the electrodes of the MOS transistor contain the same kind of impurity so as to form a single layer.

Abstract: A semiconductor device according to the present invention comprises a P-channel MOSFET having a gate, a source, and a drain, and a bipolar transistor having a collector, a base, and an emitter. The semiconductor device also includes an N.sup.- -type collector diffusion layer formed in an epitaxial layer on a P-type semiconductor substrate and adjacent to an N.sup.+ -type buried collector diffusion layer, and an N.sup.+ -type electrode lead-out region formed in contact with the N.sup.+ -type buried collector diffusion layer having an impurity concentration higher than the N.sup.- -type collector layer. A gate electrode section constituted by a gate oxide film and a gate electrode is formed on the N.sup.- -type collector layer and the N.sup.+ -type electrode lead-out region, and an P-type impurity is ion-implanted into the source region of the P-channel MOSFET and and an N-type impurity is doped into the emitter region of the bipolar transistor, with the gate electrode section being used as a mask.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer formed on the substrate, a conductive body formed on the first insulating layer, a second insulating layer formed on the first insulating layer and the conductive body and having a contact hole formed at a contact area to reach the conductive body, and a first conductive layer formed on the second insulating layer and the conductive body. The conductive body has a conductive member formed on the first insulating layer in the contact area, and a second conductive layer formed on the first insulating layer and the conductive member.

Abstract: A method for manufacturing a semiconductor device, capable of forming, with good controllability, impurity regions of a low impurity concentration, includes the steps of: forming a gate electrode on a surface of a semiconductor substrate through a gate oxide film; forming a first film on the surfaces of the gate electrode and the semiconductor substrate; forming a non-single-crystalline silicon film to cover the entire surface; forming a second film to cover the entire surface; performing anisotropic etching of the second film to form residual second films on the side walls of that step portion non-single-crystalline silicon film which is formed corresponding to a shape of the gate electrode; performing etching of the non-single-crystalline silicon film by using the residual second films as masks to form residual non-single-crystalline silicon films on the side walls of the gate electrode through the first film; ion-implanting an impurity having a conductivity type opposite to that of the semiconductor substr

Abstract: The invention provides a method for manufacturing a semiconductor device, having the steps of: forming a first mask pattern on a semiconductor layer through an SiO.sub.2 film; forming a thin layer on at least side surfaces of the first mask pattern; selectively forming a second mask pattern on an SiO.sub.2 film portion located between the thin layer portions formed on the side surface of the first mask pattern; selectively etching the thin layer portions formed on the at least side surfaces of the first mask pattern, and the SiO.sub.2 film portions under the thin layer portions formed on the side surfaces of the first mask pattern, using the first and second mask patterns; selectively etching an exposed portion of the semiconductor layer to form a trench; and forming an element isolation region by burying an insulating material in the trench.

Abstract: A method for making mask aligned narrow isolation grooves for a semiconductor device in which an insulating layer is filled in a groove of the semiconductor substrate to form an island region surrounded by the insulating layer, which comprises the steps of forming a mask pattern on a major surface of the semiconductor substrate in such a manner that its side wall is at a taper angle of 90.degree. or less with respect to a major surface of the semiconductor substrate; ion-implanting an impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate using the mask pattern; causing a groove for the insulating material to be formed in the semiconductor substrate around the side wall of the mask pattern; filling the groove with insulating material to form a narrow insulating layer; and diffusing the implanted impurity to form an isolation region surrounded by the insulating material.