Patents by Inventor Hiroshi Morioka
Hiroshi Morioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230415450Abstract: Provided is a laminate that can be pre-trimmed and can eliminate the need for a post-processing step. A laminate includes a decorative layer, an adhesive layer, and a support layer laminated in this order. The support layer includes two or more kinds of materials having different melting points including a material having a relatively low melting point and a material having a relatively high melting point.Type: ApplicationFiled: June 26, 2023Publication date: December 28, 2023Inventors: Tomonori SUGIYAMA, Kazuhiko KANEUCHI, Takashi MORIMOTO, Hiroshi MORIOKA, Hideki CHIBA, Makoto UTSUMI, Kazuya KUSU
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Patent number: 11507229Abstract: A molded body for an electronic function includes a first film in which one surface thereof constitutes an external appearance surface, a second film in which an electronic component is mounted on a surface thereof facing a surface of the first film opposite to the external appearance surface, and a first resin that fills a space between the first film and the second film. The first resin has a cavity, and the cavity is filled with a second resin, and the electronic component is disposed in the cavity and surrounded by the second resin.Type: GrantFiled: November 16, 2020Date of Patent: November 22, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroshi Morioka, Takashi Morimoto, Hideaki Eto, Tomoya Moriura, Wahei Agemizu
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Publication number: 20210388112Abstract: The present invention provides a scFv comprising a heavy chain variable region (VH) and a light chain variable region linked by a first peptide linker, wherein an N-terminus and a C-terminus thereof are linked by a second peptide linker.Type: ApplicationFiled: July 8, 2019Publication date: December 16, 2021Inventors: HIROSHI MORIOKA, YOSHIHIRO KOBASHIGAWA, TAKASHI SATO, NATSUKI FUKUDA, SOICHIRO YAMAUCHI
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Publication number: 20210157427Abstract: A molded body for an electronic function includes a first film in which one surface thereof constitutes an external appearance surface, a second film in which an electronic component is mounted on a surface thereof facing a surface of the first film opposite to the external appearance surface, and a first resin that fills a space between the first film and the second film. The first resin has a cavity, and the cavity is filled with a second resin, and the electronic component is disposed in the cavity and surrounded by the second resin.Type: ApplicationFiled: November 16, 2020Publication date: May 27, 2021Inventors: HIROSHI MORIOKA, TAKASHI MORIMOTO, HIDEAKI ETO, TOMOYA MORIURA, WAHEI AGEMIZU
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Patent number: 10962702Abstract: An input device includes: a light source that emits light; a first sheet including a design portion; a second sheet having a conductive pattern on which the light source is mounted and in which a touch sensor electrode is disposed in a position different from the light source; a body that is sandwiched between the first sheet and the second sheet to be integral therewith, and transmits the light emitted by the light source; and a guide disposed in a light path from the light source to the design portion, the guide guiding light transmitting through an inside of the body toward the design portion and being distinguished from the body. The light source and the light guide are disposed along a surface of the second sheet on a side facing the body. The body is integral with the light source and the light guide and encapsulates them.Type: GrantFiled: October 2, 2019Date of Patent: March 30, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shigeru Yamane, Hideaki Eto, Wahei Agemizu, Masahiro Kasano, Go Nakatani, Hiroshi Morioka
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Publication number: 20200110212Abstract: An input device includes: a light source that emits light; a first sheet including a design portion; a second sheet having a conductive pattern on which the light source is mounted and in which a touch sensor electrode is disposed in a position different from the light source; a body that is sandwiched between the first sheet and the second sheet to be integral therewith, and transmits the light emitted by the light source; and a guide disposed in a light path from the light source to the design portion, the guide guiding light transmitting through an inside of the body toward the design portion and being distinguished from the body. The light source and the light guide are disposed along a surface of the second sheet on a side facing the body. The body is integral with the light source and the light guide and encapsulates them.Type: ApplicationFiled: October 2, 2019Publication date: April 9, 2020Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shigeru YAMANE, Hideaki ETO, Wahei AGEMIZU, Masahiro KASANO, Go NAKATANI, Hiroshi MORIOKA
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Patent number: 9287168Abstract: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.Type: GrantFiled: April 23, 2014Date of Patent: March 15, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hiroshi Morioka, Jusuke Ogura, Sergey Pidin
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Patent number: 9224043Abstract: Performing map construction under a crowded environment where there are a lot of people. It includes a successive image acquisition unit that obtains images that are taken while a robot is moving, a local feature quantity extraction unit that extracts a quantity at each feature point from the images, a feature quantity matching unit that performs matching among the quantities in the input images, where quantities are extracted by the extraction unit, an invariant feature quantity calculation unit that calculates an average of the matched quantities among a predetermined number of images by the matching unit as an invariant feature quantity, a distance information acquisition unit that calculates distance information corresponding to each invariant feature quantity based on a position of the robot at times when the images are obtained, and a map generation unit that generates a local metrical map as a hybrid map.Type: GrantFiled: August 30, 2011Date of Patent: December 29, 2015Assignee: Tokyo Institute of TechnologyInventors: Osamu Hasegawa, Hiroshi Morioka, Noppharit Tongprasit, Sangkyu Yi
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Publication number: 20140227873Abstract: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.Type: ApplicationFiled: April 23, 2014Publication date: August 14, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: HIROSHI MORIOKA, JUSUKE OGURA, SERGEY PIDIN
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Patent number: 8749062Abstract: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.Type: GrantFiled: January 4, 2007Date of Patent: June 10, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Hiroshi Morioka, Jusuke Ogura, Sergey Pidin
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Publication number: 20130216098Abstract: Performing map construction under a crowded environment where there are a lot of people. It includes a successive image acquisition unit that obtains images that are taken while a robot is moving, a local feature quantity extraction unit that extracts a quantity at each feature point from the images, a feature quantity matching unit that performs matching among the quantities in the input images, where quantities are extracted by the extraction unit, an invariant feature quantity calculation unit that calculates an average of the matched quantities among a predetermined number of images by the matching unit as an invariant feature quantity, a distance information acquisition unit that calculates distance information corresponding to each invariant feature quantity based on a position of the robot at times when the images are obtained, and a map generation unit that generates a local metrical map as a hybrid map.Type: ApplicationFiled: August 30, 2011Publication date: August 22, 2013Applicant: Tokyo Institute of TechnologyInventors: Osamu Hasegawa, Hiroshi Morioka, Noppharit Tongprasit, Sangkyu Yi
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Patent number: 8247290Abstract: A method of manufacturing a semiconductor device has forming a first conductive film over a semiconductor substrate, etching the first conductive film, forming a plurality of first conductive patterns arranged in a first direction, and forming a side surface on an outside of a conductive pattern positioned at an end among the plurality of first conductive patterns such that the side surface has a first inclination angle smaller than a second inclination angle of a side surface on an inside of the conductive pattern positioned at the end, forming a first insulation film over the plurality of first conductive patterns, and forming a second conductive pattern over the first insulation film.Type: GrantFiled: June 27, 2008Date of Patent: August 21, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Junichi Ariyoshi, Toru Anezaki, Hiroshi Morioka
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Patent number: 7803518Abstract: A method for forming a pattern includes the steps of: (a) preparing a lower hard mask layer and an upper hard mask layer stacked on an etching target film; (b) forming a resist pattern above the upper hard mask layer; (c) etching the upper hard mask film by using the resist pattern as an etching mask to form an upper hard mask; (d) after the step (c), removing the resist pattern; (e) after the step (d), thinning the upper hard mask by etching; (f) etching the lower hard mask film by using the thinned upper hard mask as an etching mask to form a lower hard mask; and (g) etching the etching target film by using the upper hard mask and the lower hard mask as an etching mask. The method for forming a pattern can etch a fine pattern with good yield.Type: GrantFiled: April 30, 2007Date of Patent: September 28, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Hiroshi Morioka
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Patent number: 7670759Abstract: Photosensitive resist material is coated on a substrate and exposed and developed to form a resist pattern. The surface layer of sidewalls and a top wall of the resist pattern is etched by plasma of a mixture gas of a first gas and an SO2 gas, the first gas being at least one gas selected from a group consisting of He, Ne, Ar, Xe, Kr, CO, CO2 and N2. Resist pattern deformation and pattern collapse can be prevented while the resist pattern shrinks.Type: GrantFiled: October 27, 2003Date of Patent: March 2, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Hiroshi Morioka
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Patent number: 7601576Abstract: The method for fabricating a semiconductor device comprises the steps of: forming on a silicon substrate 10 a hard mask 20 of a silicon oxide film 12, and a silicon nitride film 14 having a width smaller than a width of the silicon oxide film 12; etching the silicon substrate 10 with the hard mask 20 as the mask to form a trench 26 for defining an active region 24 in the silicon substrate 10; and forming a silicon oxide film 28 on the silicon substrate 10 with the trench 26 formed in.Type: GrantFiled: November 28, 2005Date of Patent: October 13, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Rintaro Suzuki, Hiroshi Morioka, Masanori Terahara
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Patent number: 7550394Abstract: A method of fabricating a semiconductor device includes a dry etching process of a silicon surface. The dry etching process is conducted by an etching gas containing at least one gas species selected from the group consisting of: HBr, HCl, Cl2, Br2 and HI, wherein the dry etching process includes a first step conducted at a first temperature; and a second step conducted at a second temperature.Type: GrantFiled: June 6, 2005Date of Patent: June 23, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Hiroshi Morioka
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Patent number: 7501686Abstract: A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.Type: GrantFiled: February 22, 2006Date of Patent: March 10, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Masaki Okuno, Sadahiro Kishii, Hiroshi Morioka, Masanori Terahara, Shigeo Satoh, Kaina Suzuki
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Publication number: 20090042402Abstract: A semiconductor device fabrication method by which a desired pattern can be formed. After a conductive layer which is a material for a gate electrode is formed, a SiN layer to be used as a hard mask is formed. Then a photoresist layer is formed as a second mask. Then patterning is performed on the photoresist layer. Then patterning is performed on the SiN layer with the photoresist layer as a mask. After the photoresist layer is removed, surface portions of the SiN layer are transmuted and are selectively removed. The conductive layer under the SiN layer is etched with the reduced SiN layer as the hard mask. By doing so, the photoresist layer does not, for example, deform during the process and a minute gate electrode pattern can be formed stably.Type: ApplicationFiled: September 23, 2008Publication date: February 12, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Hiroshi MORIOKA
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Publication number: 20090032844Abstract: A method of manufacturing a semiconductor device has forming a transistor including a source and a drain, forming a mixed crystal layer over the source and the drain, forming a silicide layer over the mixed crystal layer, forming a first insulating film and a second insulating film over the silicide layer, forming a contact hole, performing an oxygen plasma treatment, and forming a conductive plug in the contact hole.Type: ApplicationFiled: July 29, 2008Publication date: February 5, 2009Applicants: FUJITSU LIMITED, FUJITSU MICROELECTRONICS LIMITEDInventors: Jusuke OGURA, Hikaru KOKURA, Hiroshi MORIOKA, Kazuo KAWAMURA
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Publication number: 20090001425Abstract: A method of manufacturing a semiconductor device has forming a first conductive film over a semiconductor substrate, etching the first conductive film, forming a plurality of first conductive patterns arranged in a first direction, and forming a side surface on an outside of a conductive pattern positioned at an end among the plurality of first conductive patterns such that the side surface has a first inclination angle smaller than a second inclination angle of a side surface on an inside of the conductive pattern positioned at the end, forming a first insulation film over the plurality of first conductive patterns, and forming a second conductive pattern over the first insulation film.Type: ApplicationFiled: June 27, 2008Publication date: January 1, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Junichi Ariyoshi, Toru Anezaki, Hiroshi Morioka