Patents by Inventor Hiroshi Moriya

Hiroshi Moriya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120359
    Abstract: The present disclosure relates to a photodetection device and an electronic apparatus that allow for reducing surface reflection from an on-chip microlens and suppressing deterioration of image quality. Provided is a photodetection device including: a plurality of pixels that have photoelectric conversion units; on-chip microlenses that are formed in such a way as to correspond to the individual pixels; and an antireflection film that is formed on a surface of the on-chip microlens, in which the antireflection film is constituted by a stacking of: a first inorganic film that is formed by a metal oxide film; and a second inorganic film that is formed on a surface of the first inorganic film and has a lower refractive index than the first inorganic film. The present disclosure can be applied to, for example, a CMOS solid-state imaging device.
    Type: Application
    Filed: February 21, 2022
    Publication date: April 11, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke MORIYA, Atsushi YAMAMOTO, Tomiyuki YUKAWA, Kotaro NISHIMURA, Shigehiro IKEHARA, Shogo OTANI, Hiroshi KATO
  • Patent number: 11926765
    Abstract: An adhesive composition for use in debonding with light irradiation, which composition can achieve debonding through irradiation with light, characterized in that the adhesive composition contains an adhesive component (S) and a light-absorbing organic compound (X); and the light-absorbing organic compound (X) contains, in the molecule thereof, one or more aromatic rings, one or more rings each containing a heteroatom forming the ring, and one or more groups selected from among a carbonyl group and a thiocarbonyl group.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: March 12, 2024
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Takahisa Okuno, Shunsuke Moriya, Hiroshi Ogino, Ryo Karasawa, Tetsuya Shinjo
  • Patent number: 11836923
    Abstract: An image processing apparatus according to the present invention calculates, even in a case where a region of a part as an observation target included in an image capturing range is different between a plurality of medical images in different time phases, a degree of slippage of the region of the part as the observation target with high accuracy.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: December 5, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toru Tanaka, Ryo Ishikawa, Tatsuya Kimoto, Hiroshi Moriya
  • Publication number: 20220351504
    Abstract: A method for evaluating material properties includes an image processing for evaluation step, a material properties prediction step, and an evaluation step. The image processing for evaluation step includes scanning one or more images for evaluation of a material to be evaluated, creating a low-gradation image for evaluation by lowering gradation of the image for evaluation, and creating a virtual image by processing the low-gradation image for evaluation. The material properties prediction step includes extracting features for evaluation from the low-gradation image for evaluation, predicting a first material property of the material to be evaluated from the features for evaluation through a regression model, extracting a virtual-image feature from the virtual image, and predicting a second material property of the material to be evaluated from the virtual-image features through the regression model. The evaluation step is for comparing the first material property with the second material property.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 3, 2022
    Inventors: Takahiro Yoshioka, Makoto Ono, Hiroshi Moriya, Tomohito Maki, Takahiro Yomogita
  • Patent number: 11437338
    Abstract: A method utilized at a sintered metal layer bonding a semiconductor element and a support substrate together suppresses cracks appearing in the sintered metal layer, and damage to the semiconductor element. A semiconductor device includes a support substrate, a semiconductor element, and a sintered metal layer bonding the support substrate and the semiconductor element. The sintered metal layer has a low porosity region disposed inward of an outer edge of the semiconductor element with the sintered metal layer bonded to the semiconductor element. The region is lower in porosity than the remaining sintered metal layer, and is formed as a wall-shaped structural body having an elongated string and extending from an upper surface to a lower surface of the sintered metal layer. The low porosity region is disposed to surround a region immediately below a center of the semiconductor element along the outer edge of the semiconductor element.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: September 6, 2022
    Assignee: HITACHI, LTD.
    Inventors: Tomohisa Suzuki, Hiroshi Moriya
  • Publication number: 20220084206
    Abstract: An information processing apparatus includes a first acquisition unit configured to acquire a characteristic amount relating to movement of a target site of a subject, a second acquisition unit configured to acquire a standard characteristic amount, based on a characteristic amount relating to movement of a target site of a standard subject different from the subject, and a calculation unit configured to calculate a characteristic value relating to the movement of the target site of the subject, based on the characteristic amount relating to the movement of the target site of the subject and the standard characteristic amount, wherein the second acquisition unit performs a coordinate transformation of the characteristic amount of the standard subject into a reference space, and calculates the standard characteristic amount, based on a characteristic amount resulting from the coordinate transformation.
    Type: Application
    Filed: September 7, 2021
    Publication date: March 17, 2022
    Inventors: Ryo Ishikawa, Toru Tanaka, Kiyohide Satoh, Hiroshi Moriya
  • Publication number: 20210304409
    Abstract: An image processing apparatus according to the present invention calculates, even in a case where a region of a part as an observation target included in an image capturing range is different between a plurality of medical images in different time phases, a degree of slippage of the region of the part as the observation target with high accuracy.
    Type: Application
    Filed: June 11, 2021
    Publication date: September 30, 2021
    Inventors: Toru Tanaka, Ryo Ishikawa, Tatsuya Kimoto, Hiroshi Moriya
  • Publication number: 20210265298
    Abstract: A method utilized at a sintered metal layer bonding a semiconductor element and a support substrate together suppresses cracks appearing in the sintered metal layer, and damage to the semiconductor element. A semiconductor device includes a support substrate, a semiconductor element, and a sintered metal layer bonding the support substrate and the semiconductor element. The sintered metal layer has a low porosity region disposed inward of an outer edge of the semiconductor element with the sintered metal layer bonded to the semiconductor element. The region is lower in porosity than the remaining sintered metal layer, and is formed as a wall-shaped structural body having an elongated string and extending from an upper surface to a lower surface of the sintered metal layer. The low porosity region is disposed to surround a region immediately below a center of the semiconductor element along the outer edge of the semiconductor element.
    Type: Application
    Filed: March 20, 2019
    Publication date: August 26, 2021
    Applicant: HITACHI, LTD.
    Inventors: Tomohisa SUZUKI, Hiroshi MORIYA
  • Patent number: 10364900
    Abstract: Provided are: a flow path switching valve that reduces the pressure load in a contact surface outer peripheral section of the flow path switching valve and inhibits friction between constituent components; and a liquid chromatographic device using the flow path switching valve. The flow path switching valve is provided with a stator having a plurality of through holes and a seal having conduction grooves for causing the through holes to conduct. The seal has a first portion present vertically beneath a region comprising at least a surface of contact with the stator, and a second portion having lower rigidity than the first portion, on the outside of the first portion. Due to this configuration, it is possible to reduce the pressure load when a flow path of a liquid is switched under high-pressure conditions, and inhibit the phenomenon of friction itself.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: July 30, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takaaki Hara, Hiroshi Moriya, Ayano Otsubo, Yoshihiro Nagaoka, Kiyotoshi Mori, Shoji Tomita
  • Publication number: 20160377184
    Abstract: Provided are: a flow path switching valve that reduces the pressure load in a contact surface outer peripheral section of the flow path switching valve and inhibits friction between constituent components; and a liquid chromatographic device using the flow path switching valve. The flow path switching valve is provided with a stator having a plurality of through holes and a seal having conduction grooves for causing the through holes to conduct. The seal has a first portion present vertically beneath a region comprising at least a surface of contact with the stator, and a second portion having lower rigidity than the first portion, on the outside of the first portion. Due to this configuration, it is possible to reduce the pressure load when a flow path of a liquid is switched under high-pressure conditions, and inhibit the phenomenon of friction itself.
    Type: Application
    Filed: January 22, 2015
    Publication date: December 29, 2016
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Takaaki HARA, Hiroshi MORIYA, Ayano OTSUBO, Yoshihiro NAGAOKA, Kiyotoshi MORI, Shoji TOMITA
  • Publication number: 20150028976
    Abstract: The purpose of the present invention is to provide a structure of a rare-earth magnet having high coercivity. In order to solve the problem, a rare-earth magnet according to the present invention comprises sheets of elements bonded with each other through a covalent bond 100 and layers comprising a transition metal element 200 laminated with the sheet 100, wherein a rare earth element is arranged within a plane of the sheets.
    Type: Application
    Filed: March 26, 2012
    Publication date: January 29, 2015
    Applicant: Hitachi, Ltd.
    Inventor: Hiroshi Moriya
  • Patent number: 8584152
    Abstract: The electronic device pertaining to an embodiment comprises a housing that holds an optical disk. The housing comprises a holding space holding an optical disk, a first internal space being apart from the holding space and in which a first electronic component controlling a pickup is disposed, an intake channel leading from the first internal space to the holding space, and an exhaust channel leading from the holding space to a specific space being distinct from the first internal space.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: November 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Motonari Ogura, Yukihiro Iwata, Hiroshi Moriya, Hiroki Takamori
  • Patent number: 8494019
    Abstract: Within a semiconductor laser device, mounting a semiconductor laser element array of multi-beam structure on a sub-mount, the semiconductor laser element array of multi-beam structure comprises one piece of a semiconductor substrate 11; a common electrode 1, which is formed on a first surface of the semiconductor substrate; a semiconductor layer 2, which is formed on the other surface of the semiconductor substrate, and has a plural number of light emitting portions 7 within an inside thereof; a plural number of anode electrodes 3 of a second conductivity type, which are formed above the plural number of light emitting portions, respectively; and a supporting portion 25, which is provided outside a region of forming the light emitting portions, wherein on one surface of the sub-mount is connected an electrode 3 of the semiconductor laser element array through a solder 4, and that solder 4 is formed to cover a supporting portion and an electrode neighboring thereto, and further on the electrode 3 is formed a g
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 23, 2013
    Assignee: Oclaro Japan, Inc.
    Inventors: Yoshihiko Iga, Hiroshi Moriya, Yutaka Inoue, Hideki Hara, Keiichi Miyauchi
  • Patent number: 8372693
    Abstract: In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 12, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuaki Katagiri, Hisashi Tanie, Jun Kayamori, Dai Sasaki, Hiroshi Moriya
  • Publication number: 20120302007
    Abstract: In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.
    Type: Application
    Filed: June 29, 2012
    Publication date: November 29, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Mitsuaki KATAGIRI, Hisashi TANIE, Jun KAYAMORI, Dai SASAKI, Hiroshi MORIYA
  • Patent number: 8237251
    Abstract: In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: August 7, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuaki Katagiri, Hisashi Tanie, Jun Kayamori, Dai Sasaki, Hiroshi Moriya
  • Patent number: 8049777
    Abstract: According to an insertion support system of the present invention, when a biopsy area is specified at a periphery of the bronchi, the barycenter of the biopsy area is extracted. A circle centering on the barycenter is determined as a search area. The search area is expanded until the bronchi are located within the search area. A point in the search area to which the bronchi first reach is determined as an end point. A first route choice connecting the end point and a start point is determined. If the first route choice has not been registered yet, the first route choice is registered as a first registered route. Accordingly, a location of interest can be specified as an arbitrary region, and navigation leading to the specified region is appropriately set.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: November 1, 2011
    Assignee: Olympus Corporation
    Inventors: Shunya Akimoto, Junichi Ohnishi, Fumihiro Asano, Hiroshi Moriya, Koichi Yamazaki, Takashi Ishida
  • Publication number: 20110138406
    Abstract: The electronic device pertaining to an embodiment comprises a housing that holds an optical disk. The housing comprises a holding space holding an optical disk, a first internal space being apart from the holding space and in which a first electronic component controlling a pickup is disposed, an intake channel leading from the first internal space to the holding space, and an exhaust channel leading from the holding space to a specific space being distinct from the first internal space.
    Type: Application
    Filed: January 4, 2010
    Publication date: June 9, 2011
    Inventors: Motonari Ogura, Yurihiro Iwata, Hiroshi Moriya, Hiroki Takamori
  • Publication number: 20100254421
    Abstract: Within a semiconductor laser device, mounting a semiconductor laser element array of multi-beam structure on a sub-mount, the semiconductor laser element array of multi-beam structure comprises one piece of a semiconductor substrate 11; a common electrode 1, which is formed on a first surface of the semiconductor substrate; a semiconductor layer 2, which is formed on the other surface of the semiconductor substrate, and has a plural number of light emitting portions 7 within an inside thereof; a plural number of anode electrodes 3 of a second conductivity type, which are formed above the plural number of light emitting portions, respectively; and a supporting portion 25, which is provided outside a region of forming the light emitting portions, wherein on one surface of the sub-mount is connected an electrode 3 of the semiconductor laser element array through a solder 4, and that solder 4 is formed to cover a supporting portion and an electrode neighboring thereto, and further on the electrode 3 is formed a g
    Type: Application
    Filed: March 31, 2010
    Publication date: October 7, 2010
    Inventors: Yoshihiko IGA, Hiroshi MORIYA, Yutaka INOUE, Hideki HARA, Keiichi MIYAUCHI
  • Patent number: 7792173
    Abstract: In a multi-beam semiconductor laser device, relative difference in shear strain applied to each of light-emitting portions of a laser chip mounted on a submount is suppressed, thereby reducing relative difference in polarization angle. A semiconductor laser element array mounted on a submount has a structure in which a semiconductor layer having two ridge portions is stacked on a substrate, and Au plating layers are formed on the surfaces of p type electrodes formed on the ridge portions. In each of the ridge portions, a central position of the Au plating layer in a width direction is intentionally displaced with respect to a central position of the underlying light-emitting portion in a width direction, so that shear strain is applied to each of the light-emitting portions at a stage before the semiconductor laser element array is mounted on the submount.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: September 7, 2010
    Assignee: Opnext Japan, Inc.
    Inventors: Yoshihiko Iga, Yutaka Inoue, Hiroshi Moriya, Yasuhisa Semba, Susumu Sorimachi