Abstract: In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.

Abstract: The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.

Abstract: In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.

Abstract: A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption.

Abstract: The present invention efficiently displays in a tree structure form a file operation history. A file storage identifier, an operation identifier, and a count are stored as additional meta-information in an alternate data stream with respect to each file stored in a client terminal file system. The operation identifier manages a number of operations (operation generations). The count manages copy frequencies. This meta-information is also sent to a management apparatus, and used for displaying the file operation history in a tree structure form.

Abstract: A client computer detects a user operation for transmitting data to a server or a storage device, determines whether the detected user operation is a fraudulent manipulation, and, if the determination is a positive result, performs security processing which is processing related to security of data to be transmitted. If the data is data within a group to which the user belongs and a destination of the data is a server or a storage device outside the group, the determination is a positive result.

Abstract: First, a duplicate elimination process based on a first duplicate elimination process, in which both a duplicate elimination effect and a processing load are low, is executed. Information related to a processing result of the duplicate elimination process based on the first duplicate elimination process is acquired prior to execution of a second duplicate elimination process, in which both the duplicate elimination effect and the processing load are high. Target data of the second duplicate elimination process is narrowed down based on the acquired information. The second duplicate elimination process is applied only to the narrowed down target data. As a result, an integrated duplicate elimination system with a lower processing load than in a conventional system is realized while attaining a high duplicate elimination effect.

Abstract: The content of operations is identified and an alert is generated to an operation having a high risk of information leakage. An agent monitors, for example, operations performed with respect to a dialogue displayed on a client PC. If a file is selected by an operation performed with respect to the displayed dialogue, the agent assigns an identifier indicating a source for the file to the file. If the file is sent as an attached file, the agent identifies an output destination for the attached file as well as the source for the attached file; and if the output destination for the attached file is an external Web server and the source for the attached file is a mail server, the agent generates an alert by determining that an unauthorized operation has been executed; and then sends the generated alert to a management server.

Abstract: A WEB service providing server can execute WEB service processing using data provided by an online storage service providing server, and leaking of data at the WEB service providing server can be prevented. A WEB service providing server 102 requests, in response to a service request from a client terminal 100, that an online storage service providing server 101 provides data that will satisfy the service request. The online storage service providing server 101 extracts content data from storage devices, encrypts the extracted content data, and provides the WEB service providing server 102 with storage service data composed of data including the encrypted content data and metadata. The WEB service providing server 102 constructs a WEB service screen according to the metadata and provides the client terminal 100 with the constructed WEB service screen.

Abstract: An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of input data pieces are divided into a plurality of pieces to perform an operation processing without performing the operation of the arbitrary number of input data pieces at a time. The operational circuit once stores an intermediate result for each of the divided operations in an external storage device, performs an operation processing read with an intermediate result in the next operation processing, and obtains a final result by repeating these operation processings. The operation is performed at a cyclic unit of processing corresponding to the number of address registers provided in the operational circuit.

Abstract: A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption.

Abstract: A peripheral circuit with a host load adjusting function which is capable of readily carrying out control so that the amounts of data processed by the peripheral circuit and a host CPU are balanced by limiting interrupts made by the peripheral circuit, usage of a memory bus bandwidth, and a processing throughput of data. A typical embodiment of the present invention has an adjustment limitation setting unit setting a minimum value of an interval of interrupt requests generated by the peripheral circuit with the host load adjusting function, and a cycle counter counting generation timing of the interrupt requests, and compares a value of the cycle counter with the interval set in the adjustment limitation setting unit, thereby suppressing the interrupt requests generated at an interval shorter than the set interval.

Abstract: A mobile device includes a memory for storing therein a subroutine management table to manage kinds of existing codes out of native code, first code and second code for a plurality of subroutines contained in content, a virtual machine, a precompile circuit for producing second code from first code and a subroutine management circuit for changing over processing in accordance with the kind of existing code for subroutine called up during execution of content. The subroutine management circuit judges kind of existing code with reference to the subroutine management table when the processing is changed over.

Abstract: This arithmetic logical unit outputs data to be used in checking the final result of an AES unit that encrypts a plain text block into an encrypted text block based on AES operation, and includes an arithmetic unit for computing parity data created based on XOR operation from an encryption key to be used as a key during AES encryption, parity data created based on XOR operation from a plain text block, and an AES operation halfway result output from the AES unit, and outputting a value that is equivalent to parity data created based on XOR operation from the final result of the AES unit.

Abstract: Provided is a disk array controller capable of speeding up the processing by simultaneously execution the encryption/decryption of a non parallel block cipher modes of operation. In a disk array controller for controlling a disk array according to a disk access request from a host system, a plurality of non parallel mode encryption/decryption target data are divided into a plurality of messages unrelated to the encryption/decryption processing, partitioning non parallel mode encryption/decryption target data belonging to the respective messages into a plurality of block data, storing each block data belonging to the respective messages by allocating it each line of Rnd[0] to Rnd[R?1] per message, and encrypting/decrypting block data corresponding to block data corresponding to a cell of the same column of each line among the block data stored in a data buffer simultaneously with the pipeline processing performed by a pipeline encryption/decryption circuit.

Abstract: An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of input data pieces are divided into a plurality of pieces to perform an operation processing without performing the operation of the arbitrary number of input data pieces at a time. The operational circuit once stores an intermediate result for each of the divided operations in an external storage device, performs an operation processing read with an intermediate result in the next operation processing, and obtains a final result by repeating these operation processings. The operation is performed at a cyclic unit of processing corresponding to the number of address registers provided in the operational circuit.

Abstract: In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.