Patents by Inventor Hiroshi Nakatake
Hiroshi Nakatake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10774321Abstract: A method for monomerization of MMP-7 aggregates is provided. A method for monomerization of MMP-7 aggregates which comprises treating MMP-7 aggregates with a buffer solution comprising a monovalent cation chloride (sodium chloride, potassium chloride, etc.) at a low concentration or with a buffer solution not comprising a monovalent cation chloride, a process for preparing MMP-7 which involves said method for monomerization, and a (pharmaceutical) composition comprising MMP-7 in the aforementioned buffer solution. In case that a (pharmaceutical) composition comprising MMP-7 at a low concentration is prepared, the aforementioned buffer solution comprising sugar alcohols or sugars is used.Type: GrantFiled: May 20, 2015Date of Patent: September 15, 2020Assignee: KM BIOLOGICS CO., LTD.Inventors: Hiroshi Nakatake, Masaki Hirashima, Hideki Takeo, Reiko Matsuyama, Wataru Morikawa
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Publication number: 20200140843Abstract: A method for monomerization of MMP-7 aggregates is provided. A method for monomerization of MMP-7 aggregates which comprises treating MMP-7 aggregates with a buffer solution comprising a monovalent cation chloride (sodium chloride, potassium chloride, etc.) at a low concentration or with a buffer solution not comprising a monovalent cation chloride, a process for preparing MMP-7 which involves said method for monomerization, and a (pharmaceutical) composition comprising MMP-7 in the aforementioned buffer solution. In case that a (pharmaceutical) composition comprising MMP-7 at a low concentration is prepared, the aforementioned buffer solution comprising sugar alcohols or sugars is used.Type: ApplicationFiled: January 14, 2020Publication date: May 7, 2020Applicant: THE CHEMO-SERO-THERAPEUTIC RESEARCH INSTITUTEInventors: Hiroshi NAKATAKE, Masaki HIRASHIMA, Hideki TAKEO, Reiko MATSUYAMA, Wataru MORIKAWA
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Patent number: 10038438Abstract: A driving circuit including: a voltage detector that detects the sum voltage of a positive bias voltage and a negative bias voltage, the negative bias voltage or the positive bias voltage; and a switching element that is connected to the control terminal of a power element and the negative side of a negative-voltage power supply; wherein, when the value of the detection target voltage becomes lower than a voltage setting value or when a voltage between the control terminal and the reference terminal in the power element increases in a state where the value of the detection target voltage is lower than the voltage setting value, the voltage detector turns on the switching element to thereby supply, between the above terminals in the power element, a voltage of 0V or lower.Type: GrantFiled: May 27, 2015Date of Patent: July 31, 2018Assignee: Mitsubishi Electric CorporationInventors: Kosuke Nakano, Keisuke Iwasawa, Takayoshi Miki, Hiroshi Nakatake
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Patent number: 9979314Abstract: A power semiconductor module capable of reducing variation of inductance between upper/lower arms and reducing variation of current caused by the variation of inductance. The power semiconductor module includes circuit blocks (upper/lower arms) each of which is configured by connecting self-arc-extinguishing type semiconductor elements in series; a positive electrode terminal, a negative electrode terminal, and an AC terminal that are connected to each of the circuit blocks; and wiring patterns that connect the self-arc-extinguishing type semiconductor elements of the circuit blocks to the positive electrode terminal, the negative electrode terminal, and the AC terminal, wherein the circuit block is plural in number; the positive electrode terminal, the negative electrode terminal, and the AC terminal are each disposed to be plural in number corresponding to the circuit blocks; and the positive electrode terminals and the negative electrode terminals are closely disposed.Type: GrantFiled: January 16, 2013Date of Patent: May 22, 2018Assignee: Mitsubishi Electric CorporationInventors: Yoshiko Obiraki, Yasushi Nakayama, Yuji Miyazaki, Hiroshi Nakatake
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Patent number: 9685879Abstract: A power semiconductor module capable of reducing variation of inductance between upper/lower arms and reducing variation of current caused by the variation of inductance. The power semiconductor module includes circuit blocks (upper/lower arms) each of which is configured by connecting self-arc-extinguishing type semiconductor elements in series; first and second positive electrode terminals, first and second negative electrode terminals, and first and second AC terminals. Further, there are first and second wiring patterns that connect the self-arc-extinguishing type semiconductor elements to the DC and AC terminals. The outline of the power semiconductor module has a substantially quadrangular surface.Type: GrantFiled: January 11, 2016Date of Patent: June 20, 2017Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoshiko Obiraki, Yasushi Nakayama, Yuji Miyazaki, Hiroshi Nakatake
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Patent number: 9608618Abstract: A temperature detection circuit for detecting a temperature of a switching element, a current source for causing a forward current to flow to the temperature detection circuit, an amplifier circuit for amplifying a forward voltage of the temperature detection circuit, a current adjustment circuit for adjusting a magnitude of a gate current to the switching element on the basis of an output voltage of the amplifier circuit, and a drive circuit for receiving an external signal and turning ON/OFF the switching element, are included. The magnitude of the gate current caused to flow from the current adjustment circuit to the gate electrode of the switching element is adjusted on the basis of a change in a magnitude of the forward voltage corresponding to a change in the temperature of the temperature detection circuit.Type: GrantFiled: January 29, 2014Date of Patent: March 28, 2017Assignee: Mitsubishi Electric CorporationInventors: Takuya Sakai, Hiroshi Nakatake
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Publication number: 20170081654Abstract: A method for monomerization of MMP-7 aggregates is provided. A method for monomerization of MMP-7 aggregates which comprises treating MMP-7 aggregates with a buffer solution comprising a monovalent cation chloride (sodium chloride, potassium chloride, etc.) at a low concentration or with a buffer solution not comprising a monovalent cation chloride, a process for preparing MMP-7 which involves said method for monomerization, and a (pharmaceutical) composition comprising MMP-7 in the aforementioned buffer solution. In case that a (pharmaceutical) composition comprising MMP-7 at a low concentration is prepared, the aforementioned buffer solution comprising sugar alcohols or sugars is used.Type: ApplicationFiled: May 20, 2015Publication date: March 23, 2017Applicant: THE CHEMO-SERO-THERAPEUTIC RESEARCH INSTITUTEInventors: Hiroshi NAKATAKE, Masaki HIRASHIMA, Hideki TAKEO, Reiko MATSUYAMA, Wataru MORIKAWA
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Publication number: 20170040992Abstract: A driving circuit including: a voltage detector that detects the sum voltage of a positive bias voltage and a negative bias voltage, the negative bias voltage or the positive bias voltage; and a switching element that is connected to the control terminal of a power element and the negative side of a negative-voltage power supply; wherein, when the value of the detection target voltage becomes lower than a voltage setting value or when a voltage between the control terminal and the reference terminal in the power element increases in a state where the value of the detection target voltage is lower than the voltage setting value, the voltage detector turns on the switching element to thereby supply, between the above terminals in the power element, a voltage of 0V or lower.Type: ApplicationFiled: May 27, 2015Publication date: February 9, 2017Applicant: Mitsubishi Electric CorporationInventors: Kosuke NAKANO, Keisuke IWASAWA, Takayoshi MIKI, Hiroshi NAKATAKE
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Publication number: 20160172995Abstract: A power semiconductor module capable of reducing variation of inductance between upper/lower arms and reducing variation of current caused by the variation of inductance. The power semiconductor module includes circuit blocks (upper/lower arms) each of which is configured by connecting self-arc-extinguishing type semiconductor elements in series; first and second positive electrode terminals, first and second negative electrode terminals, and first and second AC terminals. Further, there are first and second wiring patterns that connect the self-arc-extinguishing type semiconductor elements to the DC and AC terminals. The outline of the power semiconductor module has a substantially quadrangular surface.Type: ApplicationFiled: January 11, 2016Publication date: June 16, 2016Applicant: Mitsubishi Electric CorporationInventors: Yoshiko Obiraki, Yasushi Nakayama, Yuji Miyazaki, Hiroshi Nakatake
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Publication number: 20150358013Abstract: A temperature detection circuit for detecting a temperature of a switching element, a current source for causing a forward current to flow to the temperature detection circuit, an amplifier circuit for amplifying a forward voltage of the temperature detection circuit, a current adjustment circuit for adjusting a magnitude of a gate current to the switching element on the basis of an output voltage of the amplifier circuit, and a drive circuit for receiving an external signal and turning ON/OFF the switching element, are included. The magnitude of the gate current caused to flow from the current adjustment circuit to the gate electrode of the switching element is adjusted on the basis of a change in a magnitude of the forward voltage corresponding to a change in the temperature of the temperature detection circuit.Type: ApplicationFiled: January 29, 2014Publication date: December 10, 2015Applicant: Mitsubishi Electric CorporationInventors: Takuya SAKAI, Hiroshi NAKATAKE
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Patent number: 9184739Abstract: A gate drive circuit for driving an IGBT serving as a power semiconductor device includes a constant-current gate drive circuit that charges a gate capacity of the IGBT at a constant current, and a constant-voltage gate drive circuit that is connected in parallel to the constant-current gate drive circuit between input and output terminals thereof via a series circuit constituted by a MOSFET and a resistor, and charges the gate capacity of the IGBT at a constant voltage, wherein the gate drive circuit charges the gate capacity of the IGBT using both the constant-current gate drive circuit and the constant-voltage gate drive circuit at the time of driving the IGBT.Type: GrantFiled: June 9, 2011Date of Patent: November 10, 2015Assignee: Mitsubishi Electric CorporationInventors: Masashi Kaneko, Shizuri Tamura, Hiroshi Nakatake
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Publication number: 20150023081Abstract: A power semiconductor module capable of reducing variation of inductance between upper/lower arms and reducing variation of current caused by the variation of inductance. The power semiconductor module includes circuit blocks (upper/lower arms) each of which is configured by connecting self-arc-extinguishing type semiconductor elements in series; a positive electrode terminal, a negative electrode terminal, and an AC terminal that are connected to each of the circuit blocks; and wiring patterns that connect the self-arc-extinguishing type semiconductor elements of the circuit blocks to the positive electrode terminal, the negative electrode terminal, and the AC terminal, wherein the circuit block is plural in number; the positive electrode terminal, the negative electrode terminal, and the AC terminal are each disposed to be plural in number corresponding to the circuit blocks; and the positive electrode terminals and the negative electrode terminals are closely disposed.Type: ApplicationFiled: January 16, 2013Publication date: January 22, 2015Applicant: Mitsubishi Electric CorporationInventors: Yoshiko Obiraki, Yasushi Nakayama, Yuji Miyazaki, Hiroshi Nakatake
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Patent number: 8803508Abstract: In a semiconductor device utilizing a power semiconductor element provided with a main cell and a current sensing cell, a load overcurrent is accurately detected and a short circuit current is rapidly detected. The output of a current sensing cell is connected to an inverting input terminal of an operational amplifier, and a non-inverting input terminal of the operational amplifier is connected to the source of the main cell. A current/voltage conversion circuit configured with the operational amplifier and a sensing resistor converts an output current of the current sensing cell into a sensing voltage. A first error detection circuit compares the sensing voltage with a first reference voltage and outputs an error signal. A second error detection circuit compares a voltage at the inverting input terminal of the operational amplifier with a second reference voltage set to be higher than a source-bias voltage and outputs an error signal.Type: GrantFiled: June 17, 2010Date of Patent: August 12, 2014Assignee: Mitsubishi Electric CorporationInventor: Hiroshi Nakatake
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Patent number: 8785931Abstract: A semiconductor device capable of rapidly and accurately sensing the information regarding the temperature of a semiconductor transistor contained therein. A MOSFET includes a plurality of cells, and includes a main cell group including a cell for supplying a current to a load among the plurality of cells, and a sense cell group including a cell for sensing temperature information regarding the temperature of the MOSFET thereamong. The main cell group and the sense cell group have different temperature characteristics showing changes in electrical characteristics to changes in temperature. A temperature sensing circuit senses the temperature of the MOSFET based on, for example, a value of a main current flowing through the main cell group and a value of a sense current flowing through the sense cell group.Type: GrantFiled: August 26, 2011Date of Patent: July 22, 2014Assignee: Mitsubishi Electric CorporationInventors: Shinichi Kinouchi, Hiroshi Nakatake, Yuji Ebiike, Akihiko Furukawa, Masayuki Imaizumi
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Patent number: 8748132Abstract: A process for preparing an inclusion body-forming protein is provided. A nucleic acid fragment having a nucleotide sequence coding for a modified alkaline phosphatase signal peptide (modified APSP) where leucine at the 13th position in the amino acid sequence shown in SEQ ID NO: 1 is substituted with proline and/or alanine at the 21st position is substituted with the other amino acid, downstream of which nucleotide sequence is bound a nucleotide sequence of a gene of a protein of interest is also provided.Type: GrantFiled: October 21, 2009Date of Patent: June 10, 2014Assignees: The Chemo-Sero-Therapeutic Research Institute, Teijin Pharma LimitedInventors: Hiroshi Nakatake, Akihiro Meta, Kiyotaka Suenaga, Masaki Hirashima, Hiroaki Maeda
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Patent number: 8679783Abstract: A Factor X (hereinafter referred to as “FX”) with a high activity is provided. The present invention relates to a method for efficiently preparing a recombinant, two-chain FX which comprises intervening glycosylation at such an amino acid sequence that is essential for glycosylation in FX to thereby allow for expression of a recombinant FX with no glycosylation, and the recombinant FX with no glycosylation obtained by said method.Type: GrantFiled: February 24, 2012Date of Patent: March 25, 2014Assignee: The Chemo-Sero-Therapeutic Research InstituteInventors: Kenji Soejima, Takayuki Imamura, Ryoichi Kawamura, Hiroshi Nakatake, Arisa Maeyashiki, Hitomi Togo
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Publication number: 20140055190Abstract: A gate drive circuit for driving an IGBT serving as a power semiconductor device includes a constant-current gate drive circuit that charges a gate capacity of the IGBT at a constant current, and a constant-voltage gate drive circuit that is connected in parallel to the constant-current gate drive circuit between input and output terminals thereof via a series circuit constituted by a MOSFET and a resistor, and charges the gate capacity of the IGBT at a constant voltage, wherein the gate drive circuit charges the gate capacity of the IGBT using both the constant-current gate drive circuit and the constant-voltage gate drive circuit at the time of driving the IGBT.Type: ApplicationFiled: June 9, 2011Publication date: February 27, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Masashi Kaneko, Shizuri Tamura, Hiroshi Nakatake
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Patent number: 8598920Abstract: A gate driving circuit for driving a voltage-driven switching device is provided with a current limiting circuit for limiting a gate current ig that flows into a gate terminal through a gate resistor at turn-on to a current limit value IL which defines an upper limit value. The current limit value IL is set at a value which is larger than a gate current value I2 at turn-on of the switching device during a period when the Miller effect occurs but is smaller than a gate current value I1 at a point in time when a main current begins to flow at turn-on in a case where the gate current ig is not limited by the current limiting circuit. This arrangement makes a variation in a collector current of the switching device moderate at turn-on thereof when the collector current begins to flow, thereby reducing high-frequency noise.Type: GrantFiled: May 7, 2010Date of Patent: December 3, 2013Assignee: Mitsubishi Electric CorporationInventors: Hiroshi Nakatake, Shinichi Kinouchi, Tatsuya Kitamura
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Patent number: 8519751Abstract: A gate drive circuit capable of turning on a semiconductor switching element at high speed, which includes: a buffer circuit including a turn-on-drive switching element and a turn-off-drive switching element that are complementarily turned on and off, for driving the semiconductor switching element; a first DC voltage supply including a positive electrode connected to the source or emitter of the turn-on-drive switching element and a negative electrode connected to a reference potential; and a second DC voltage supply including a positive electrode connected to the source or emitter of the turn-off-drive switching element and a negative electrode connected to the reference potential.Type: GrantFiled: September 2, 2010Date of Patent: August 27, 2013Assignee: Mitsubishi Electric CorporationInventors: Tatsuya Kitamura, Hiroshi Nakatake, Yasushi Nakayama
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Publication number: 20130153900Abstract: A semiconductor device capable of rapidly and accurately sensing the information regarding the temperature of a semiconductor transistor contained therein. A MOSFET includes a plurality of cells, and includes a main cell group including a cell for supplying a current to a load among the plurality of cells, and a sense cell group including a cell for sensing temperature information regarding the temperature of the MOSFET thereamong. The main cell group and the sense cell group have different temperature characteristics showing changes in electrical characteristics to changes in temperature. A temperature sensing circuit senses the temperature of the MOSFET based on, for example, a value of a main current flowing through the main cell group and a value of a sense current flowing through the sense cell group.Type: ApplicationFiled: August 26, 2011Publication date: June 20, 2013Applicant: Mitsubishi Electric CorporationInventors: Shinichi Kinouchi, Hiroshi Nakatake, Yuji Ebiike, Akihiko Furukawa, Masayuki Imaizumi