Patents by Inventor Hiroshi Nakatani

Hiroshi Nakatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160054671
    Abstract: The present invention is to provide a toner that has a total volatile organic component content (TVOC content) reduced to a low level, is less likely to cause fog even when used in either a low-temperature and low-humidity environment or a high-temperature and high-humidity environment, does not cause filming even in continuous printing, and is excellent in printing durability.
    Type: Application
    Filed: March 26, 2014
    Publication date: February 25, 2016
    Applicant: ZEON CORPORATION
    Inventors: Takeru CHIBA, Hiroshi NAKATANI
  • Publication number: 20160048089
    Abstract: The present invention is to provide a toner which is able to inhibit the occurrence of fog, which is excellent in intermittent endurance, and which is excellent in followability during toner transfer and is thus excellent in top edge part uniformity in solid pattern printing. Disclosed is a toner for developing electrostatic images, comprising colored resin particles containing a binder resin, a colorant and a release agent, and an external additive, wherein static and kinetic friction coefficients obtained by measuring, using a 3-mm-diameter stainless-steel ball as a contactor, a 55-mm-diameter disk-shaped pellet obtained by pressing 4 g of the toner at 9 MPa for one minute, are 0.220 to 0.320 and 0.190 to 0.270, respectively, and a difference calculated by subtracting the kinetic friction coefficient from the static friction coefficient is 0.010 to 0.090.
    Type: Application
    Filed: March 5, 2014
    Publication date: February 18, 2016
    Applicant: ZEON CORPORATION
    Inventors: Hiroshi Nakatani, Takeru Chiba
  • Publication number: 20160004177
    Abstract: Disclosed is an electrostatic image developer containing colored resin particles containing a binder resin and a colorant, and an external additive, wherein, as the external additive, the electrostatic image developer contains plate-shaped zinc oxide fine particles having an average longer length of 50 to 2,000 nm and a value S of 0.0001 to 0.03 nm?1, which is a value obtained by dividing an average thickness d of the particles by an average base area A of the particles, and a content of the plate-shaped zinc oxide fine particles is in the range from 0.05 to 1 part by mass, with respect to 100 parts by mass of the colored resin particles.
    Type: Application
    Filed: February 21, 2014
    Publication date: January 7, 2016
    Applicant: ZEON CORPORATION
    Inventors: Takeru Chiba, Hiroshi Nakatani
  • Publication number: 20150249764
    Abstract: An image forming apparatus includes a registration roller configured to adjust a starting time point of conveying a paper sheet; a printing unit configured to form a color image or a monochrome image on a photosensitive drum, and transfer the image to the paper sheet at a downstream side with respect to the registration roller in a conveyance direction to print; a line sensor configured to detect a conveyance position at an upstream side with respect to the printing unit in the conveyance direction; and a control unit configured to obtain a displacement amount with respect to a preset reference position based on the conveyance position, correct an image formation position according to the displacement amount to correct a printing position on the paper sheet, and change a correction method for the printing position according to whether any of the color image and the monochrome image is formed.
    Type: Application
    Filed: September 9, 2013
    Publication date: September 3, 2015
    Inventors: Hiroshi Nakatani, Norio Tomita, Ryosuke Sakai
  • Patent number: 9069318
    Abstract: An image forming apparatus includes an image forming portion that forms an image on a recording sheet, a transport path that transports the recording sheet with the image formed thereon by the image forming portion, a coating portion that performs a coating process that forms a coating film on the recording sheet that is being transported on the transport path, and a reading portion that reads a calibration chart on the recording sheet that is being transported on the transport path. The coating portion is disposed on the upstream side in a recording sheet transport direction of the reading portion on the transport path, a calibration process is performed for an image formed by the image forming portion, and the calibration chart is formed on the recording sheet by the image forming portion in order to perform the calibration process.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: June 30, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Norio Tomita, Hiroshi Nakatani, Ryosuke Sakai, Takumi Mori, Kyosuke Taka, Kohichi Yamauchi
  • Publication number: 20150081041
    Abstract: According to one embodiment, there is provided an output apparatus including a signal control unit configured to set a signal from a second output element in an OFF state at a timing earlier than a predetermined timing by the response time of a second load, and set signals from a first output element and the second output element in an ON state, and signals from a first interruption element and a second interruption element in an OFF state at a timing earlier than the predetermined timing by the response time of a first load. The output apparatus includes a diagnosis unit configured to diagnose, at the predetermined timing, whether the first and second interruption elements are in a normal state or a failure state, based on a signal from the first and second digital output circuits.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 19, 2015
    Inventors: Fumitaka Mouri, Makoto Toko, Hiroshi Nakatani, Naoya Ohnishi, Akira Nojima
  • Publication number: 20150044604
    Abstract: The present invention provides a toner for developing electrostatic images, which is configured to keep excellent heat-resistant storage stability, increase charge stability against environmental changes, and show excellent stability even after a long period of storage. Disclosed is a toner for developing electrostatic images, comprising an external additive and colored resin particles comprising a binder resin, a colorant and a charge control agent, wherein the charge control agent is a positively-chargeable charge control agent, and wherein the toner further contains 80 to 500 ppm of a cyano group-containing hydrocarbon compound having a molecular weight of 100 to 300.
    Type: Application
    Filed: February 27, 2013
    Publication date: February 12, 2015
    Applicant: ZEON CORPORATION
    Inventors: Hiromichi Jin, Hiroshi Nakatani
  • Patent number: 8780421
    Abstract: A transparent sheet is attached onto an inclined surface of an original guide plate of an image reading apparatus, and similarly, a transparent sheet is attached onto an inclined surface at an edge portion of a reading guide plate, thereby preventing an original from being chipped by the ground glass-like inclined surfaces and illumination light from being diffused by the ground glass-like inclined surfaces.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: July 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenji Nakanishi, Hiroshi Nakatani, Hisashi Yamanaka, Shohichi Fukutome, Yoshihisa Yamada, Masahiro Imoto, Yasuhiro Suto
  • Patent number: 8776071
    Abstract: A microprocessor operation monitoring system whose own tasks are constituted by associating beforehand the task number of the task that is next to be started up, for each of the tasks constituting the program, and abnormality of microprocessor operation is detected by comparing and determining whether or not the announced task and the task to be started up match.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Inoue, Jun Takehara, Hiroshi Nakatani, Motohiko Okabe, Yasutaka Umeda
  • Patent number: 8762926
    Abstract: An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Nakatani, Naoya Ohnishi, Satoru Amaki, Yoshito Sameda, Makoto Toko
  • Patent number: 8762788
    Abstract: A redundancy control system and method of transmitting computational data are provided, for detection of transmission errors and failure diagnosis, including generating first computational data and generating first generated data using a first generation algorithm for error detection; generating second computational data and generating second generated data using a second generation algorithm for error detection; comparing the first/second computational data; transmitting transmission data including coincident computational data and the first/second generated data; generating, in the receiving device, computational data and third/fourth generated data from preset first/second generation algorithms; and comparing the first/third generated data and the first/third generated data, and detecting the presence or absence of an error in the received computational data.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Nakatani, Naoya Ohnishi, Makoto Toko, Motohiko Okabe
  • Patent number: 8717066
    Abstract: A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 6, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoya Ohnishi, Hiroshi Nakatani, Yoshito Sameda, Jun Takehara, Makoto Toko
  • Publication number: 20140095949
    Abstract: An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.
    Type: Application
    Filed: January 30, 2013
    Publication date: April 3, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi NAKATANI, Naoya OHNISHI, Satoru AMAKI, Yoshito SAMEDA, Makoto TOKO
  • Patent number: 8516310
    Abstract: The embodiments provide a failure diagnosis method for a main memory in an information processing device equipped with a write-back cache. According to the method, an application program stored in the main memory is divided by the storage size of write-back cache, and the regions are stored in advance. Then, a read signal from the main memory to the write-back cache is detected. It is determined whether the region corresponding to the read signal has yet to be diagnosed. If the region has yet to be diagnosed, a command to diagnose failure of the region is issued. If a write signal (write back) to a particular region is detected during the diagnosis of the particular region, the diagnosis of the particular region is stopped. Thus, the failure diagnosis of the main memory is executed in parallel with the execution of the application program.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoya Ohnishi, Hiroshi Nakatani, Yoshito Sameda
  • Patent number: 8504871
    Abstract: A safety output includes an output controller to make an instruction to output normal output data and first self-diagnosis pattern data synchronously with a control cycle, a normal output unit to output the normal output data synchronously with the control cycle, a test pattern generating unit to encode the self-diagnosis pattern data into a pulse train signal having a pulse width not larger than a preset value and output the pulse train signal in accordance with a baseband transmission system, a combination output unit to combine the pulse train signal with the normal output signal and output the resultant signal, a reconfiguration unit to decode the inputted operation-terminal-portion output signal to reconfigure the operation-terminal-portion output signal as second self-diagnosis pattern data, and a comparator to compare the first self-diagnosis pattern data with the second self-diagnosis pattern data to judge the presence or absence of a difference.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Nakatani, Makoto Toko, Eigo Fukai
  • Patent number: 8479064
    Abstract: A safety input device includes an input controller to control transmission of an input signal to an arithmetic device, an output controller to instruct output of preset first self-diagnosis pattern data, a test pattern generating unit to encode the first self-diagnosis pattern data into a pulse train signal having a pulse width equal to or below a predetermined value and output the pulse train signal, a combination input unit to combine the pulse train signal with the input signal, an input interface unit, a pattern reconfiguration unit to decode an output signal from the combination input unit into second self-diagnosis pattern data, and a comparator to compare the first and second self-diagnosis pattern data to judge the presence or absence of a difference between the first and second self-diagnosis pattern data.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: July 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Nakatani, Makoto Toko, Eigo Fukai
  • Patent number: 8471440
    Abstract: A magnetic head driving piezoelectric ceramic actuator having an actuator body and a coating layer. The actuator body has a piezoelectric ceramic substrate and first and second electrodes. The piezoelectric ceramic substrate has first and second principal surfaces, first and second side surfaces, and first and second edge surfaces. The first electrode has a first external electrode portion formed on a part of the first principal surface, and a second external electrode portion formed on the first edge surface. The second electrode has a third external electrode portion formed on the second edge surface, and a fourth external electrode portion formed on the first principal surface. Each of: at least a part of each of the first and second external electrode portions; and at least a part of each of the third and fourth external electrode portions, constitutes a joined portion mounted on the substrate by an electrically-conductive agent.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: June 25, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroshi Nakatani, Masanaga Nishikawa
  • Patent number: 8416476
    Abstract: A first reading guide includes a first guide member, which can turn around a first shaft and is so positioned as to face a first side of a document. The second reading guide includes a second guide member, which can turn around a second shaft and is so positioned as to face a second side of a document. The distance between a first reading position and a reference position is equal to that between a second reading position and the reference position. The first shaft is positioned on the side of the reference position where the first reading position is set. The second shaft is positioned on the side of the reference position where the second reading position is set.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: April 9, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masato Tamehira, Hiroshi Nakatani
  • Publication number: 20130082739
    Abstract: A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.
    Type: Application
    Filed: September 13, 2012
    Publication date: April 4, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoya OHNISHI, Hiroshi Nakatani, Yoshito Sameda, Jun Takehara, Makoto Toko
  • Publication number: 20130051817
    Abstract: An image forming apparatus includes an image forming portion that forms an image on a recording sheet, a transport path that transports the recording sheet with the image formed thereon by the image forming portion, a coating portion that performs a coating process that forms a coating film on the recording sheet that is being transported on the transport path, and a reading portion that reads a calibration chart on the recording sheet that is being transported on the transport path. The coating portion is disposed on the upstream side in a recording sheet transport direction of the reading portion on the transport path, a calibration process is performed for an image formed by the image forming portion, and the calibration chart is formed on the recording sheet by the image forming portion in order to perform the calibration process.
    Type: Application
    Filed: July 11, 2012
    Publication date: February 28, 2013
    Inventors: Norio TOMITA, Hiroshi NAKATANI, Ryosuke SAKAI, Takumi MORI, Kyosuke TAKA, Kohichi YAMAUCHI