Patents by Inventor Hiroshi Namba

Hiroshi Namba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146580
    Abstract: An estimation system generates, from a value of a time series of an estimation object in a past period, a plurality of patterns of a transition of a value of the estimation object. Based on the plurality of generated patterns and a value of a time series of a factor in the past period, the estimation system specifies a dependency relationship between a transition pattern and a value of the factor and a transition pattern at a past (or future) time point and identifies a model in accordance with the specified dependency relationship. By inputting a value of a time series of the factor in a future period to the estimation model, the estimation system specifies a time series of a value in the future period of the estimation object using at least one transition pattern.
    Type: Application
    Filed: March 8, 2022
    Publication date: May 2, 2024
    Inventors: Masato UTSUMI, Tohru WATANABE, Kazuki NAMBA, Ikuo SHIGEMORI, Hiroshi IIMURA, Hiroaki OGAWA, Daisuke HAMABA, Jun YAMAZAKI
  • Patent number: 8507377
    Abstract: A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: August 13, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
  • Publication number: 20100240211
    Abstract: A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.
    Type: Application
    Filed: April 21, 2010
    Publication date: September 23, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kenichi WATANABE, Michiari KAWANO, Hiroshi NAMBA, Kazuo SUKEGAWA, Takumi HASEGAWA, Toyoji SAWADA
  • Patent number: 7755169
    Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: July 13, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
  • Publication number: 20090127666
    Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.
    Type: Application
    Filed: January 22, 2009
    Publication date: May 21, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kenichi WATANABE, Michiari KAWANO, Hiroshi NAMBA, Kazuo SUKEGAWA, Takumi HASEGAWA, Toyoji SAWADA, Junichi Mitani
  • Patent number: 7498659
    Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: March 3, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
  • Patent number: 7129565
    Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: October 31, 2006
    Assignee: Fujitsu Limited
    Inventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
  • Publication number: 20060194124
    Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.
    Type: Application
    Filed: February 13, 2006
    Publication date: August 31, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
  • Publication number: 20030173675
    Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.
    Type: Application
    Filed: January 24, 2003
    Publication date: September 18, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada, Junichi Mitani
  • Patent number: 4300556
    Abstract: A facial beauty device attainable, in addition to facial sauna effect with a heated and highly moistened atmosphere, a facial skin washing effect by means of water spray and simultaneously both facial skin tightening and massaging effects accompanying inherent cooling and spray pressure, respectively. The device is provided with a moistening means oscillating water in a reservoir within a body case at a frequency of an ultrasonic band and delivering generated mist into a hood on the case to provide a highly moistened atmosphere within the hood, means for heating the mist by passing it through an electric resistive heater or carrying it onto the hood with hot air stream heated by the heater, and means for spraying water in the reservoir or from a tank capable of automatically supplying water responsive to falling water level in the reservoir toward a face contacting opening of the hood through nozzles opened in the hood by means of a pump.
    Type: Grant
    Filed: July 25, 1980
    Date of Patent: November 17, 1981
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Shuhei Ochi, Fumiya Ueda, Nobuyuki Morihara, Hiroshi Namba, Motohisa Nishino, Shigeo Yamamoto