Abstract: An instruction memory circuit comprises an external instruction memory for storing a plurality of instruction codes, and an internal instruction memory having capability of outputting and rewriting instruction codes stored therein at high speed for storing instruction codes which have preliminarily been read out from the external instruction memory and outputting the instruction codes for instruction execution. The internal instruction memory is composed of 1st through Nth memory blocks which can be accessed independently. The instruction memory circuit also comprises a memory block reading measure and a memory block writing measure. The memory block reading measure activates one of the 1st through Nth memory blocks for instruction code reading, and executes instruction code reading from the activated memory block.

Abstract: A serial interface circuit for performing operations in a plurality of modes is disclosed, which includes an input terminal supplied with a serial data, a first shift register fetching and shifting data at the input terminal in synchronism with a clock signal, a selector for selecting the input terminal in a first mode and an output of the first shift register in a second mode, a second shift register fetching and shifting data at an output of the selector, a set of first output terminals, a set of second output terminals, and an output control circuit outputting first data derived in parallel from the first shift register and second data derived in parallel from the second shift register to the first and second output terminals in the second mode and one of the first and second data to one of the first and second output terminals in the first mode. The respective operations in the first and second modes are thus performed. The output control is favorably incorporated with a bit order reversing function.