Patents by Inventor Hiroshi Narahashi

Hiroshi Narahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11842938
    Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 12, 2023
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Publication number: 20220235470
    Abstract: A method for fabricating a semiconductor device comprises depositing a TiW layer on a semiconductor substrate, depositing a Ti layer on the TiW layer, depositing a Ni alloy layer on the Ti layer, depositing an Ag layer on the Ni alloy layer, at least partially covering the Ag layer with photoresist, wet etching the Ag layer and the Ni alloy layer, and dry etching the Ti layer and the TiW layer.
    Type: Application
    Filed: January 24, 2022
    Publication date: July 28, 2022
    Inventors: Saurabh Roy, Matteo Dainese, Michael Ehmann, Hiroshi Narahashi, Johanna Schlaminger, Katharina Teichmann, Sigrid Wabnig
  • Publication number: 20220093483
    Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 24, 2022
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Patent number: 11217500
    Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: January 4, 2022
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Publication number: 20190311966
    Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 10, 2019
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert