Patents by Inventor Hiroshi Nittaya

Hiroshi Nittaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020008820
    Abstract: A liquid crystal display apparatus which has a liquid crystal display and a controller. The liquid crystal display has a plurality of rectangular pixels arranged in a matrix, a plurality of scanning electrodes extending in the direction parallel to the longer sides of the rectangular pixels, a plurality of signal electrodes extending in the direction orthogonal to the longer sides of the rectangular pixels. The controller is to drive the scanning electrodes and the signal electrodes. An image is written on the liquid crystal display by using a driving pulse for carrying out writing after resetting the liquid crystal and by carrying out interlace scanning with one frame divided into a plurality of fields. The pixel pitch in the vertical direction is 1/n (for example, 1/1.5) of the pixel pitch in the horizontal direction. If the pixel pitch in the vertical direction is 1/1.
    Type: Application
    Filed: June 26, 2001
    Publication date: January 24, 2002
    Applicant: MINOLTA CO., LTD.
    Inventors: Tsukasa Yagi, Masaaki Nakai, Eiji Yamakawa, Kazuaki Okumura, Hiroshi Nittaya, Katsuhiko Asai
  • Patent number: 5737251
    Abstract: A rank order filter is disclosed in which the maximum value, the minimum value and the median value are determined in a 3.times.3 local area having three sample values in each of column and row. The three sample values in the 3.times.3 local area are rearranged in descending order of magnitude by column, and the maximum values or the minimum values in each column are compared with each other thereby to determine the maximum value or the minimum value in the 3.times.3 local area. Also, after comparing the median values with each other in each column, the maximum value in the column having the minimum median value, the minimum value in the column having the maximum median value and the median value in the column having the median median value are compared with each other. The result of comparison is used to determine the median value in the 3.times.3 local area.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: April 7, 1998
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventors: Masahiro Kohno, Hiroshi Nittaya, Masahiro Kato
  • Patent number: 5532948
    Abstract: A rank order filter is disclosed in which the maximum value, the minimum value and the median value are determined in a 3.times.3 local area having three sample values in each of column and row. The three sample values in the 3.times.3 local area are rearranged in descending order of magnitude by column, and the maximum values or the minimum values in each column are compared with each other thereby to determine the maximum value or the minimum value in the 3.times.3 local area. Also, after comparing the median values with each other in each column, the maximum value in the column having the minimum median value, the minimum value in the column having the maximum median value and the median value in the column having the median median value are compared with each other. The result of comparison is used to determine the median value in the 3.times.3 local area.
    Type: Grant
    Filed: January 6, 1994
    Date of Patent: July 2, 1996
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventors: Masahiro Kohno, Hiroshi Nittaya, Masahiro Kato
  • Patent number: 5432619
    Abstract: A labeling method and a labeling apparatus thereof, whereby a primary label of a binary image is determined and a primary label for the following image is prepared in accordance with the combination of the data of four adjacent images P(i,j), P(i,j+1), p(i+1,j) and P(i+1,j+1) with simpler hardwares.
    Type: Grant
    Filed: December 22, 1992
    Date of Patent: July 11, 1995
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventors: Hiroshi Nittaya, Masahiro Kohno, Takurou Teragaki
  • Patent number: 5341324
    Abstract: A gate electrode of a P-channel MOS transistor and a gate electrode of an N-channel MOS transistor which constitute a logic section, a gate electrode of an N-channel MOS transistor and a capacitor electrode which constitute a memory cell section are formed by patterning a first layer of polysilicon, so that the semiconductor device can be manufactured in a considerably simplified process as an SRAM, while taking advantage of the large capacity of a DRAM thereby to improve the yield.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: August 23, 1994
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventors: Toshiyuki Matsumoto, Hirofumi Inada, Hiroshi Nittaya, Masahiro Kato
  • Patent number: 5136505
    Abstract: In an electronic translator apparatus, synonymous phrases (title data) and sentences in plural languages are stored in correspondence to each other. These phrases or sentences are read out and translated. This electronic translator apparatus stores the title data as a basic phrase and the explanatory data relating to the title data, thereby allowing a wide range of translation. The title data can be translated into plural languages which are displayed simultaneously. The title data and corresponding sentences are separately stored, thereby increasing the number of sentences that can be translated. The display method is varied depending on the necessity. If the sentence to be translated is long, part of the original sentence during displaying is ommitted and the translated sentence is displayed in whole. When translating into English, an article may be added or a plural form may be expressed so as to translate properly.
    Type: Grant
    Filed: August 3, 1989
    Date of Patent: August 4, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimitsu Inamori, Hiroshi Takada, Masao Okumura, Toshiro Oba, Hiroshi Nittaya, Shuji Kaya, Fumiaki Kawawaki, Tetsuya Inoue, Michiaki Kuno, Hisao Kunita
  • Patent number: 4564954
    Abstract: A speech synthesizer may generate random sounds during die-down after power turn-off. To prevent such sound generation, the synthesizer clock circuit is grounded by an FET simultaneously with power turn-off.
    Type: Grant
    Filed: January 5, 1983
    Date of Patent: January 14, 1986
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Nittaya, Kosuke Nishimura
  • Patent number: 4540180
    Abstract: An electronic game apparatus independently provided or to be incorporated into an electronic calculator, timepiece, or the like comprises a game start circuit, a game setting circuit, a memory, a search circuit, an indication circuit, a comparison circuit, a bombardment circuit, and a display. The game start circuit is operated to start a game. The game setting circuit is provided for setting a matrix size and for setting at least one target therein. The memory is provided for storing the matrix size and the target position. The search circuit is provided for searching the target position by a search area. The indication circuit is provided for indicating whether the target is positioned inside the search area. The bombardment circuit is provided for inputting the target position data searched. The comparison circuit is provided for comparing the target position and the target position data searched. The display is provided for displaying the game data used for these circuits.
    Type: Grant
    Filed: August 10, 1983
    Date of Patent: September 10, 1985
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akitaka Morita, Hiroshi Nittaya