Abstract: A semiconductor device includes a conductive substrate, a conductive first joint portion arranged on the substrate, a SiC diode chip arranged on the first joint portion, a conductive second joint portion arranged on the SiC diode chip, and a transistor chip arranged on the second joint portion. The SiC diode chip includes a cathode pad arranged on one end and an anode pad arranged on the other end in the thickness direction. The cathode pad is joined to the substrate by the first joint portion. The transistor chip includes a drain electrode arranged on one end in the thickness direction. The anode pad is joined with the drain electrode by the second joint portion. The anode pad is arranged in a region enclosed by an outer edge of the SiC diode chip as viewed in a thickness direction of the substrate. The anode pad has an area larger than that of the transistor chip as viewed in the thickness direction of the substrate.

Abstract: A semiconductor device includes a semiconductor chip made of material containing silicon carbide, a base plate including a plate-shaped insulating body and metal layers disposed on opposite faces thereof, and a bonding material bonding the semiconductor chip on one face of the base plate, wherein the bonding material is made of a metal material whose post-bonding melting point is greater than or equal to 773° C., wherein a thickness of the bonding material is less than or equal to 50 micrometers, wherein a thickness of the base plate is greater than or equal to 500 micrometers, and wherein with a thickness of the insulating body being denoted as tI, and a thickness of each of the metal layers being denoted as tM, a value of tI/tM is greater than or equal to 4.3.

Abstract: A semiconductor device includes a semiconductor chip made of material containing silicon carbide, a base plate including a plate-shaped insulating body and metal layers disposed on opposite faces thereof, and a bonding material bonding the semiconductor chip on one face of the base plate, wherein the bonding material is made of a metal material whose post-bonding melting point is greater than or equal to 773° C., wherein a thickness of the bonding material is less than or equal to 50 micrometers, wherein a thickness of the base plate is greater than or equal to 500 micrometers, and wherein with a thickness of the insulating body being denoted as tI, and a thickness of each of the metal layers being denoted as tM, a value of tI/tM is greater than or equal to 4.3.

Abstract: Inexpensive production is achieved while avoiding the degradation of electrical performance caused by the lowering of heat dissipation. The base plate 11 used here has a linear expansion coefficient of 2 to 10 ppm/K, which differs from the linear expansion coefficient of the semiconductor chip 13 by an absolute value of 7 ppm/K or smaller. The bonding layer 12 is formed such that the thickness b thereof is 50 micrometers or smaller, which is thinner than the thickness c of the semiconductor chip 13. Since the thickness b of the bonding layer 12 is thinner than the thickness c of the semiconductor chip 13, the bonding layer 12 upon the heating of the semiconductor chip 13 exhibits thermal expansion that is of relatively small significance, and thus follows the expansion and contraction of the base plate 11.

Abstract: Inexpensive production is achieved while avoiding the degradation of electrical performance caused by the lowering of heat dissipation. The base plate 11 used here has a linear expansion coefficient of 2 to 10 ppm/K, which differs from the linear expansion coefficient of the semiconductor chip 13 by an absolute value of 7 ppm/K or smaller. The bonding layer 12 is formed such that the thickness b thereof is 50 micrometers or smaller, which is thinner than the thickness c of the semiconductor chip 13. Since the thickness b of the bonding layer 12 is thinner than the thickness c of the semiconductor chip 13, the bonding layer 12 upon the heating of the semiconductor chip 13 exhibits thermal expansion that is of relatively small significance, and thus follows the expansion and contraction of the base plate 11.

Abstract: A semiconductor device which can improve its reliability and a method for manufacturing the same are provided. A semiconductor device (10) in accordance with one embodiment comprises a semiconductor element (12), a substrate (20), a case (40), and a sealant injection path (50). The semiconductor element (12) is mounted to the substrate (20). The case (40) contains the substrate (20) and allows a sealant to be injected therein for sealing the semiconductor element (12) to the inside. The sealant injection path (50) is formed in the case (40) and used for injecting the sealant into the case (40). In the sealant injection path (50), an injection port within the case (40) for the sealant is located on the substrate (20) side of an injection region (44) of the sealant within the case (40).

Abstract: A semiconductor device includes at least one semiconductor chip, a gate wiring connected to the at least one semiconductor chip, a first wiring connected to the at least one semiconductor chip, and a second wiring connected to the at least one semiconductor chip. The first and second wirings extend along the gate wiring. The first wiring is arranged between the gate wiring and second wiring. The first wiring is the wiring closest to the gate wiring. A first part of the gate wiring opposing the first wiring is shorter than a second part of the gate wiring opposing the second wiring.

Abstract: A semiconductor device includes a semiconductor chip, a die pad having a chip mount surface for mounting the semiconductor chip, and an electrode terminal for connecting with the semiconductor chip through first and second wirings. The electrode terminal has a first surface including a connection point with the first wiring and a second surface including a connection point with the second wiring. The connection point with the first wiring is located at a first height from a reference plane extending from the chip mount surface. The connection point with the second wiring is located at a second height different from the first height from the reference plane.

Abstract: A semiconductor device includes at least one semiconductor chip, a gate wiring connected to the at least one semiconductor chip, a first wiring connected to the at least one semiconductor chip, and a second wiring connected to the at least one semiconductor chip. The first and second wirings extend along the gate wiring. The first wiring is arranged between the gate wiring and second wiring. The first wiring is the wiring closest to the gate wiring. A first part of the gate wiring opposing the first wiring is shorter than a second part of the gate wiring opposing the second wiring.

Abstract: A semiconductor device according to an embodiment includes: first and second semiconductor chips, each including a first electrode and a second electrode opposite to each other in a predetermined direction; a chip-mount substrate on which the first and second semiconductor chips are mounted; and a first wiring terminal to which the second electrodes of the first and second semiconductor chips are connected. The second semiconductor chip lies over the first semiconductor chip in the predetermined direction such that the second electrode of the first semiconductor chip and the second electrode of the second semiconductor chip face each other across the first wiring terminal, and the chip-mount substrate is bent such that the first electrode of the first semiconductor chip is connected to the first electrode of the second semiconductor chip.

Abstract: A semiconductor device includes a semiconductor chip, a die pad having a chip mount surface for mounting the semiconductor chip, and an electrode terminal for connecting with the semiconductor chip through first and second wirings. The electrode terminal has a first surface including a connection point with the first wiring and a second surface including a connection point with the second wiring. The connection point with the first wiring is located at a first height from a reference plane extending from the chip mount surface. The connection point with the second wiring is located at a second height different from the first height from the reference plane.

Abstract: A semiconductor device in one embodiment includes a chip-mount substrate, a first semiconductor chip mounted on the chip-mount substrate, and a second semiconductor chip mounted adjacent to the first semiconductor chip on the chip-mount substrate. The chip-mount substrate has a first surface on which the first semiconductor chip is mounted, and a second surface on which the second semiconductor chip is mounted. The second surface and the first surface are at different positions in a thickness direction of the chip-mount substrate.

Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, a gate electrode terminal, and a die pad. The first semiconductor chip has a first gate electrode pad and a second gate electrode pad electrically connected to the first gate electrode pad. The second semiconductor chip has a gate electrode pad connected to the second gate electrode pad via a wiring. The gate electrode terminal is connected to the first gate electrode pad of the first semiconductor chip via a wiring. The die pad has a chip mounting surface for mounting the first and second semiconductor chips.

Abstract: A silicon carbide substrate includes a base layer made of silicon carbide, silicon carbide layers made of single-crystal silicon carbide and arranged side by side on the base layer when viewed in plan view, and a filling portion made of silicon carbide and filling a gap formed between the adjacent silicon carbide layers. The filling portion has a surface roughness of not more than 50 ?m in RMS value.