Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

Abstract: A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

Abstract: A pattern forming apparatus using lithography technique includes a stage configured to allow a target object to be placed thereon; a plurality of columns configured to form patterns on the target object by using a charged particle beam while moving relatively to the stage; a pattern forming rule setting unit configured to set a pattern forming rule depending on a position of broken one of the plurality of columns; a region setting unit configured to set regions so that unbroken ones of the plurality of columns respectively form a pattern in one of the regions; a plurality of control circuits each configured to control any one of the plurality of columns different from others of the plurality of columns controlled by others of the plurality of control circuits; and a pattern forming data processing unit configured to perform a converting process on pattern forming data for the regions set to output a corresponding data generated by the converting process to the control circuit of a corresponding one of the unb

Abstract: A pattern forming apparatus using lithography technique includes a stage configured to allow a target object to be placed thereon; a plurality of columns configured to form patterns on the target object by using a charged particle beam while moving relatively to the stage; a pattern forming rule setting unit configured to set a pattern forming rule depending on a position of broken one of the plurality of columns; a region setting unit configured to set regions so that unbroken ones of the plurality of columns respectively form a pattern in one of the regions; a plurality of control circuits each configured to control any one of the plurality of columns different from others of the plurality of columns controlled by others of the plurality of control circuits; and a pattern forming data processing unit configured to perform a converting process on pattern forming data for the regions set to output a corresponding data generated by the converting process to the control circuit of a corresponding one of the unb

Abstract: A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

Abstract: It is an object of the present invention to effectively manufacture a charged-particle beam lithography mask, an X-ray lithography mask, or an extreme ultraviolet beam lithography mask by using, for example, an existing writer such as an electron beam writer for photomasks, while achieving improvement in processing accuracy of a mask pattern. A lithography mask (1) comprises a substrate (2) which has a lower surface provided substantially at the center thereof with an opening (3) and a self-supporting membrane (m) having a pattern region (4) substantially at the center of an upper surface of the substrate (2) corresponding to the opening (3). The self-supporting membrane (m) is provided with through-holes (h) of a mask pattern in it or an absorber or scatterer of a mask pattern on it, and the pattern region (4) and a peripheral region around the pattern region (5) are in one plane.

Abstract: A cord type thermal fuse, comprising a fuse core produced by winding a conductor meltable at a predetermined temperature on an insulating core member continuous in the length direction, and an insulating cover covering the outer periphery of the fuse core, wherein the conductor can be cut by expanding the insulating core member at a predetermined temperature and/or by contracting the insulating cover at the predetermined temperature.

Abstract: It is an object of the present invention to effectively manufacture a charged-particle beam lithography mask, an X-ray lithography mask, or an extreme ultraviolet beam lithography mask by using, for example, an existing writer such as an electron beam writer for photomasks, while achieving improvement in processing accuracy of a mask pattern. A lithography mask (1) comprises a substrate (2) which has a lower surface provided substantially at the center thereof with an opening (3) and a self-supporting membrane (m) having a pattern region (4) substantially at the center of an upper surface of the substrate (2) corresponding to the opening (3). The self-supporting membrane (m) is provided with through-holes (h) of a mask pattern in it or an absorber or scatterer of a mask pattern on it, and the pattern region (4) and a peripheral region around the pattern region (5) are in one plane.

Abstract: A code type thermal fuse, comprising a fuse core produced by winding a conductor meltable at a predetermined temperature on an insulating core member continuous in the length direction, and an insulating cover covering the outer periphery of the fuse core, wherein the conductor can be cut by expanding the insulating core member at a predetermined temperature and/or by contracting the insulating cover at the predetermined temperature.

Abstract: The present invention consists in a method of creating an EB mask for electron beam image drawing, comprising: a step of extracting patterns for forming on an EB mask from design data stored in means for storage; a step of calculating an aperture area of an aperture section requested in an EB mask, using the design data contained in the extracted cell; a step of generating cell data for aperture creation using the value of this aperture area; and a step of forming a basic aperture pattern in an EB mask using this cell data for aperture creation.

Abstract: There is provided a method of aligning a semiconductor substrate with a base stage on which the semiconductor substrate is placed, in the process of forming a circuit pattern directly onto the semiconductor substrate with electron beams, the method including the steps of (a) scanning across an alignment mark formed on a surface of the semiconductor substrate with electron beams with a scanning angle, defined as an angle between a direction of the electron beams and a reference direction, being varied, (b) calculating a width of the alignment mark along a scanning direction for each of scanning angles, and (c) determining a minimum width among widths calculated in the step (b), and defining a scanning angle associated with the minimum width as an angular gap between the semiconductor substrate and the base stage.

Abstract: An electron-beam exposure mask that is able to realize the required pattern transfer accuracy independent of the deflection distortion and aberration of an electron beam. This mask includes a substrate with a first area and a second area, a first plurality of cell apertures formed in the first area of the substrate, and a second plurality of cell apertures formed in the second area of the substrate. The first area of the substrate is designed so that a charged-beam irradiated to the first area has a deflection angle less than a reference angle. The second area of the substrate is designed so that a charged-beam irradiated to the second area has a deflection angle equal to or greater than the reference angle. Each of the first plurality of cell apertures corresponds to fine patterns necessitating high pattern transfer accuracy. Each of the second plurality of cell apertures corresponds to rough patterns unnecessitating the high pattern transfer accuracy.

Abstract: A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched.

Abstract: Disclosed herein is a method of electron beam cell projection lithography, employing an electron beam which is shaped by a first aperture having a first opening and a second aperture having a plurality of second openings. The shaped electron beam is irradiated on a sample surface to expose plurality of patterns on the sample surface, wherein an exposure dose is determined according to an exposure intensity distribution function, thereby correcting a proximity effect, while the exposure dose is also controlled to correct for a beam blur induced by a Coulomb interaction effect. The exposure intensity distribution function includes a term for correcting the Coulomb interaction effect.

Abstract: The aperture structure is for cell projection writing of patterns on a semiconductor substrate by an electron beam. The aperture structure includes a wafer, and a plurality of aperture patterns formed in the wafer. The aperture patterns are positioned and structured such that a thermal coefficient of a front side of the wafer and that of a back side of the wafer are the same as each other. The aperture patterns are positioned in a central portion and are symmetrically shaped in the depth direction of the base. For fabricating the aperture structure, the front side of the wafer is etched, or the front side and the back side of the wafer are etched, and the aperture patterns are formed in the etched portion or portions. The back side of the wafer is etched to the same depth as the front side. The aperture structure does not become warped, and the accuracy of generating patterns on a wafer with electron beams is greatly enhanced.

Abstract: A bus interface is connected to a system bus for monitoring a bus command indicating that data is updated on a cache memory of a processor. If the data is updated on the cache memory, the external tag storage device stores state information to indicate the update of the data and a physical address corresponding to the updated data. An external tag reading device reads the state information stored in the external tag storage device, when the updated data on the cache memory is stored in a main memory. A bus command for flushing the updated data from the cache memory to the main memory is generated, based on the state of the tag read out from the external tag storage device. An invalid bus command generation device outputs an invalid bus command to the system bus through a FIFO.

Abstract: An apparatus for exposing a semiconductor wafer to light, includes a light source, a glass substrate, a mask having thereon a first pattern composed of light-impermeable material, a projection lens, and an illumination optical system for radiating light derived from the light source to said mask to thereby transfer the pattern on a semiconductor wafer. The glass substrate constitutes a part of the illumination optical system and has a plurality of second patterns which are light-permeable and each of which has a different dimension from each other. The second patterns preferably are square in shape, and also preferably a combination of squares and equilateral triangles in shape.

Abstract: A method for writing on a semiconductor wafer using electron beams is provided. One embodiment of the method includes the steps of using electron beams to irradiate a semiconductor substrate on which a resist layer has been formed, to thereby draw patterns on the resist layer, and then baking the resist layer and substrate in a vacuum.