Patents by Inventor Hiroshi Odaira
Hiroshi Odaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100242270Abstract: A manufacturing method for a wiring circuit board includes the steps of: forming a board on a surface of a metal layer directly or indirectly through an etching barrier layer; forming an insulating film on the surface of the metal layer; polishing the insulating film to an extent to which a top face of the bump is exposed; and forming a solder ball on the top face of the bump.Type: ApplicationFiled: February 16, 2010Publication date: September 30, 2010Inventors: Tomoo Iijima, Kimitaka Endo, Kazuo Ikenaga, Hiroshi Odaira, Naoto Minari, Takashi Kato
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Publication number: 20080264678Abstract: The connection resistance between a metal bump (8) and a metal layer (10) for forming a wiring film deposited later is further decreased, the connection stability is enhanced, the wiring path passing through the metal bump (8) is further shortened, the planarity is enhanced, and the metal bump (8) does not come out easily. A wiring film interconnecting member wherein a plurality of pillar-like metal bumps (8) composed of copper and having a cross-sectional area of the top surface smaller than that of the bottom surface and interconnecting the wiring films of a multilayer wiring board are buried in an interlayer insulation film (10) in such a way that at least one end projects. The upper surface of the interlayer insulation film (10) is so curved as to be high at a part in contact with the metal bump (8) and lower gradually as being farther therefrom.Type: ApplicationFiled: September 6, 2005Publication date: October 30, 2008Applicant: Tessera Interconnect Materials, Inc.Inventors: Tomoo lijima, Hiroshi Odaira, Tomokazu Shimada, Akifumi Iijima
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Publication number: 20050097727Abstract: A plurality of multi-layer metal plates (1) each being composed of a bump forming metal layer (2), an etching stop layer (3), and a wiring film forming metal layer (4), and in which a wiring film (4a) is formed from the wiring film forming metal layer and a bump 2a is formed from the bump forming metal layer are prepared, and on a bump forming surface of a multi-layer metal plate, a wiring film of another multi-layer metal plate is overlapped. Such lamination process is repeated in succession for multi-layering. In addition, a polishing machine for multi-layer wiring board (11a) which includes metal plate holding means (13) for holding a metal plate (1a), cutter holding means (25) for holding a cutter (26) above the metal plate, height adjustment mechanism (20) for adjusting the height of the cutter holding means, and cutter parallel moving mechanism (15) for relatively moving the cutter holding means in parallel to the surface of the metal plate is used to conduct polishing.Type: ApplicationFiled: March 27, 2002Publication date: May 12, 2005Inventors: Tomoo Iijima, Yoshiro Kato, Hiroshi Odaira, Masayuki Ohsawa, Inetaro Kurosawa, Kazuo Sakuma, Toshihiko Asano, Kimitaka Endo
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Publication number: 20040201096Abstract: An object of the present invention is to reduce the number of steps necessary for connecting between a wiring circuit board and a printed circuit board and to achieve a low-cost wiring circuit board. A wiring circuit board (2) includes an insulating film (4), a bump (6), an etching barrier layer (8), and a wiring layer (10). The bump (6) is made of copper and formed to penetrate through the insulating film (4). A top face of the bump (6) is exposed at a surface of the insulating film (4) flush therewith. The etching barrier layer (8) is made of nickel (Ni) and formed underneath the bump (6). The bump (6) is connected to the wiring layer (10) through the etching barrier layer (8). A solder ball (12) is formed on the top face of the bump (6). A printed circuit board (14) as a rigid board is connected to the wiring circuit board (2). A wiring layer (16) is connected to the bump (6) through the solder ball (12) to thereby mount the wiring circuit board (2) to the printed circuit board (14).Type: ApplicationFiled: March 30, 2004Publication date: October 14, 2004Inventors: Tomoo Iijima, Kimitaka Endo, Kazuo Ikenaga, Hiroshi Odaira, Naoto Minari, Takashi Kato
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Patent number: 6010769Abstract: A multilayered wiring board using conductive pillars for the interconnection of wiring layers. Since through holes are bored in the via lands of the wiring layers of the multilayered wiring board, the stress applied between the conductive pillars and wiring layers can be released at the time of connecting the conductive pillars to the via lands. Since the external side face of each conductive pillar smoothly continues to the surface of the via land at the contact section between the conductive pillar and the via land, the notch effect is relieved. Therefore, the reliability of the interconnection is secured even when a stress is applied to the connections during the manufacturing of the multilayered wiring board, and the mounting of electronic elements, etc.Type: GrantFiled: July 16, 1997Date of Patent: January 4, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Sasaoka, Hiroshi Odaira, Madoka Fujiwara, Fumitoshi Ikegaya, Takahiro Mori
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Patent number: 5973395Abstract: An IC package is provided that has a flexible wiring sheet, including an upper portion, a lower portion and a side portion which is wound around a base member over an upper surface, side surfaces and a lower surface of the base member. An IC is loaded on an upper surface of the upper flexible wiring sheet covering the upper surface of the base member. The IC is connected to an electrode provided on an upper lead pattern portion laid along the upper surface of the flexible wiring sheet. The lead pattern is extended from the upper flexible wiring sheet to the lower flexible wiring sheet via the side surfaces of the flexible wiring sheet covering side surfaces of the base member. An electrode to be connected with an object is arranged on the lower lead pattern portion which is formed on the lower flexible wiring sheet, and overall the IC or an IC connection portion is sealed on the upper surface of the upper flexible wiring sheet.Type: GrantFiled: April 29, 1997Date of Patent: October 26, 1999Assignee: Yamaichi Electronics Co., Ltd.Inventors: Etsuji Suzuki, Akira Yonezawa, Hidehisa Yamazaki, Hiroshi Odaira
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Patent number: 5955780Abstract: A contact converting structure of a semiconductor chip comprises a semiconductor chip with a group of electrodes arranged on a surface of one side thereof. A liquid crystal polymer film is bonded to the surface in such a manner as to cover the electrodes group, and a group of external contacts is arranged on the other surface of the semiconductor chip. The external contacts group is connected to the electrodes group through the liquid crystal polymer film. A process for manufacturing a semiconductor chip having such a contact converting structure is also disclosed.Type: GrantFiled: April 21, 1998Date of Patent: September 21, 1999Assignee: Yamaichi Electronics Co., Ltd.Inventors: Etsuji Suzuki, Hiroshi Odaira, Eiji Imamura
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Patent number: 5822850Abstract: A supporting member or first synthetic resin sheet with conductive bumps disposed at predetermined positions are superposed on a second synthetic resin sheet under the condition that the resin component of the second synthetic resin sheet is plastic deformed or the temperature thereof exceeds a glass transition temperature so that the conductive bumps are pierced into the second synthetic resin sheet. In other words, the conductive bumps are pierced vertically into the second synthetic resin sheet so as to form through-type conducive lead portions exposed to the first (supporting substrate) and second synthetic resin sheets. The through-type conductive lead portions are used to electrically connect electric devices and circuit and to connect wiring pattern layers. The conductive bumps can be precisely and densely formed and disposed by printing method or plating method. The conductive bumps can be pushed and pierced into the second synthetic resin sheet.Type: GrantFiled: December 22, 1995Date of Patent: October 20, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Odaira, Eiji Imamura, Yusuke Wada, Yasushi Arai, Kenji Sasaoka, Takahiro Mori, Fumitoshi Ikegaya, Sadao Kowatari
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Patent number: 5600103Abstract: A supporting member or first synthetic resin sheet with conductive bumps disposed at predetermined positions are superposed on a second synthetic resin sheet under the condition that the resin component of the second synthetic resin sheet is plastic deformed or the temperature thereof exceeds a glass transition temperature so that the conductive bumps are pierced into the second synthetic resin sheet. In other words, the conductive bumps are pierced vertically into the second synthetic resin sheet so as to form through-type conducive lead portions exposed to the first (supporting substrate) and second synthetic resin sheets. The through-type conductive lead portions are used to electrically connect electric devices and circuit and to connect wiring pattern layers. The conductive bumps can be precisely and densely formed and disposed by printing method or plating method. The conductive bumps can be pushed and pierced into the second synthetic resin sheet.Type: GrantFiled: March 2, 1994Date of Patent: February 4, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Odaira, Eiji Imamura, Yusuke Wada, Yasushi Arai, Kenji Sasaoka, Takahiro Mori, Fumitoshi Ikegaya, Sadao Kowatari
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Patent number: 5407557Abstract: A multi-layer wiring board where a plurality of wiring boards are laminated. The wiring board comprises a flexible insulating layer having a through hole and a wiring pattern formed on the flexible insulating layer. The wiring pattern is composed at least of two conductive layers. The first conductive layer formed on the insulating layer is made of a non-metallic conductor and the first wiring pattern is formed by a laser beam. The second conductive layer is an electroplated layer formed on the first wiring pattern. The first and second conductive layers have different reflectance for a beam.Type: GrantFiled: February 24, 1994Date of Patent: April 18, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Iida, Hiroshi Odaira, Yoshizumi Sato, Yuichi Yamamoto
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Patent number: 5333379Abstract: Small projections are arranged on a molding surface of at least one of an upper die half and a lower die half constituting a molding die, and a predetermined number of conductor circuits each including small projections are formed on the molding surface by electrically plating. A predetermined number of conductor circuits are formed on the molding surface of other die half in the same manner. Subsequently, the molding surfaces of both the die halves are brought in pressure contact with each other so that the electrically plated layers each including small projections on the molding surface are connected electrically. Thereafter, the hollow space between both the die halves is filled with a predetermined resin, whereby the conductor circuits are reversely secured to the resultant molded product to complete production of a three-dimensional wiring board. After electronic components are assembled on the three-dimensional wiring board, the resin is removed from the molded product by dissolving the resin.Type: GrantFiled: April 6, 1992Date of Patent: August 2, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Odaira, Yoshizumi Sato
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Patent number: 5310966Abstract: A multi-layer wiring board where a plurality of wiring boards are laminated. The wiring board comprises a flexible insulating layer having a through hole and a wiring pattern formed on the flexible insulating layer. The wiring pattern is composed at least of two conductive layers. The first conductive layer formed on the insulating layer is made of a non-metallic conductor and the first wiring pattern is formed by a laser beam. The second conductive layer is an electroplated layer formed on the first wiring pattern. The first and second conductive layers have different reflectance for a beam.Type: GrantFiled: January 5, 1993Date of Patent: May 10, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Iida, Hiroshi Odaira, Yoshizumi Sato, Yuichi Yamamoto
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Patent number: 4395109Abstract: An electronic duplicator machine heats a toner attached to a copying paper and a fixing device fixes the toner to the paper. The fixing device includes a heat generating roller which includes a supporting body having a journal portion on either end surface and rotatably supported by the journal portion; a heat insulating layer formed on the outer circumferential surface of the supporting body to prevent the transmission of heat to the supporting body; a resistance heater layer through which a current flows to heat the toner and which covers the outer circumferential surface of the heat insulating layer.Type: GrantFiled: June 5, 1980Date of Patent: July 26, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Shunichi Nakajima, Hiroshi Odaira