Abstract: In a system for encoding, transmitting, and decoding data in real time, irrespective of the jittering in a transmission path and the encoding bit rate used, synchronization is established between encoder end decoder ends with ease and reliability in the present invention. A change of a difference ‘d’ between STC (output value of STC counter) at the decoder end and SCR extracted from an encoding stream (MPEG2-PS) is integrated over a given time. Depending on whether the integrated value is positive or negative, a determination is made whether the data processing speed at the decoder end is faster than the encoder end. When the integrated value is positive, the input clock frequency of the STC counter at the decoder end is reduced, and when the integrated value is negative, the input clock frequency thereof is increased.

Abstract: In a system for encoding, transmitting, and decoding data in real time, synchronization is established between encoder end decoder ends with ease and reliability no matter if jittering occurs in a transmission path and no matter what encoding bit rate is used. A change of a difference d between STC (output value of STC counter) at the decoder end and SCR extracted from an encoding stream (MPEG2-PS) is integrated over a given time. Depending on whether the integrated value is positive or negative, a determination is made whether the data processing speed at the decoder end is faster than the encoder end. When the integrated value is positive, the input clock frequency of the STC counter at the decoder end is reduced, and when the integrated value is negative, the input clock frequency thereof is increased.

Abstract: A clock generation circuit for a digital video processing apparatus which has a simple structure and can be stably worked in both luminance and color signal systems. A color burst phase error signal indicative of phase difference of a color burst signal is produced on the basis of two color difference signals, a sampling clock signal is generated in accordance with the color burst phase error signal, the sampling clock is divided in order to produce a chrominance subcarrier signal, and the phase of the chrominance subcarrier signal is adjusted in accordance with the color burst phase error signal.