Patents by Inventor Hiroshi Oji

Hiroshi Oji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112996
    Abstract: A semiconductor device includes: a substrate having an obverse and a reverse face; wirings on the obverse face such as a first and a second drive wiring; a semiconductor element connected to the first and second drive wirings; a first drive conductor on the same side as the semiconductor element with respect to the substrate outside of the semiconductor element as viewed in a thickness direction and connected to the first drive wiring; a second drive conductor on the same side as the semiconductor element with respect to the substrate outside of the semiconductor element as viewed in the thickness direction and connected to the second drive wiring; and a sealing resin covering the wirings and the semiconductor element, while also covering the first and second drive conductor such that their faces opposite to the substrate in the thickness direction are exposed. The first and the second drive conductor are separated in a direction parallel to the obverse face.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 4, 2024
    Inventors: Hiroshi OJI, Hiroyuki SHINKAI, Natsuki SAKAMOTO, Naoyuki SANO
  • Patent number: 11088065
    Abstract: A semiconductor device comprising: substrate having main surface facing thickness direction; wirings arranged on main surface; semiconductor element having back surface facing the main surface and electrodes formed on back surface, wherein the electrodes are bonded to the wirings; and columnar wirings located outside the semiconductor element as viewed along the thickness direction, protrude in direction away from the main surface in the thickness direction, and are arranged on the wirings, wherein the semiconductor element includes first circuit and second circuit, wherein the electrodes include first electrodes electrically connected to the first circuit and second electrodes electrically connected to the second circuit, wherein the columnar wirings include first columnar portions electrically connected to the first electrodes and second columnar portions electrically connected to the second electrodes, and wherein area of each first columnar portions is larger than area of each second columnar portions in
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 10, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Hiroshi Oji
  • Publication number: 20200294902
    Abstract: A semiconductor device comprising: substrate having main surface facing thickness direction; wirings arranged on main surface; semiconductor element having back surface facing the main surface and electrodes formed on back surface, wherein the electrodes are bonded to the wirings; and columnar wirings located outside the semiconductor element as viewed along the thickness direction, protrude in direction away from the main surface in the thickness direction, and are arranged on the wirings, wherein the semiconductor element includes first circuit and second circuit, wherein the electrodes include first electrodes electrically connected to the first circuit and second electrodes electrically connected to the second circuit, wherein the columnar wirings include first columnar portions electrically connected to the first electrodes and second columnar portions electrically connected to the second electrodes, and wherein area of each first columnar portions is larger than area of each second columnar portions in
    Type: Application
    Filed: December 4, 2019
    Publication date: September 17, 2020
    Inventor: Hiroshi OJI
  • Patent number: 8536681
    Abstract: A MOS integrated circuit including an N-type silicide MOS transistor, an N-type non-silicide MOS transistor simultaneously formed with the N-type silicide MOS transistor, and an isolation film having an N conductivity type impurity formed on the N-type non-silicide MOS transistor.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: September 17, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Hiroshi Oji
  • Publication number: 20110037127
    Abstract: A MOS integrated circuit including an N-type silicide MOS transistor, an N-type non-silicide MOS transistor simultaneously formed with the N-type silicide MOS transistor, and an isolation film having an N conductivity type impurity formed on the N-type non-silicide MOS transistor.
    Type: Application
    Filed: October 28, 2010
    Publication date: February 17, 2011
    Applicant: ROHM CO., LTD.
    Inventor: Hiroshi OJI
  • Patent number: 7683432
    Abstract: A semiconductor device having a high-K gate dielectric layer includes a p-type well that is formed in an upper layer of a silicon substrate. Arsenic ions are implanted into an extreme surface layer of the p-type well and a heat treatment is performed to form a p-type low-concentration layer. A HfAlOx film and a polycrystalline silicon layer are laminated on the substrate. A gate electrode is formed by patterning the polycrystalline silicon layer. After a n-type extension region is formed by implanting arsenic ions by using the gate electrode as a mask, sidewall spacers are formed on sides of the gate electrode. Arsenic ions are implanted by using the sidewall spacers and the gate electrode as masks, whereby n-type source/drain regions are formed.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: March 23, 2010
    Assignee: Rohm Co., Ltd.
    Inventor: Hiroshi Oji
  • Publication number: 20090057739
    Abstract: The Ge channel device comprises: a Ge channel layer (2); a Si-containing interface layer (4) formed on the Ge channel layer (2); a La2O3 layer (6) formed on the interface layer (4); and an electrically conductive layer (8) formed on the La2O3 layer (6). In this device, the Si-containing interface layer (4) functions to suppress the diffusion of Ge atoms into the La2O3 layer (6) and thereby prevents the formation of Ge oxide in the La2O3 layer (6); accordingly, a Ge channel device whose C-V characteristic exhibits only a small hysteresis can be achieved.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Applicant: Tokyo Institute of Technology
    Inventors: Hiroshi Iwai, Takeo Hattori, Kazuo Tsutsui, Kuniyuki Kakushima, Parhat Ahmet, Jaeyeol Song, Masaki Yoshimaru, Yasuyoshi Mishima, Tomonori Aoyama, Hiroshi Oji, Yoshitake Kato
  • Publication number: 20090011555
    Abstract: In a method of manufacturing a CMOS integrated circuit according to the present invention, a PSD step (step of forming P-type source/drain regions) is first carried out, and an NSD step (step of forming N-type source/drain regions) is thereafter carried out, in order to create a mixed structure of a silicide transistor and a non-silicide transistor. Thus, a step of depositing an oxide film on a substrate surface may be carried out only once, the oxide film can be removed by a single step of etching with hydrofluoric acid, and the operating characteristics of formed devices can be excellently maintained.
    Type: Application
    Filed: July 1, 2008
    Publication date: January 8, 2009
    Applicant: ROHM CO., LTD.
    Inventor: Hiroshi Oji
  • Publication number: 20080230842
    Abstract: A semiconductor device having a high-K gate dielectric layer includes a p-type well that is formed in an upper layer of a silicon substrate. Arsenic ions are implanted into an extreme surface layer of the p-type well and a heat treatment is performed to form a p-type low-concentration layer. A HfAlOx film and a polycrystalline silicon layer are laminated on the substrate. A gate electrode is formed by patterning the polycrystalline silicon layer. After a n-type extension region is formed by implanting arsenic ions by using the gate electrode as a mask, sidewall spacers are formed on sides of the gate electrode. Arsenic ions are implanted by using the sidewall spacers and the gate electrode as masks, whereby n-type source/drain regions are formed.
    Type: Application
    Filed: June 20, 2005
    Publication date: September 25, 2008
    Inventor: Hiroshi Oji
  • Patent number: 5869862
    Abstract: Control gate electrodes 12 are formed on field oxidation layers 19. Anisotropic etching is carried out by covering all the regions except for a source region by photo-resist layers 31 and using the control gate electrodes 12 as a mask. Concave parts 20 are formed in the inner side of the control gate electrodes 12 of the field oxidation layer 19. A source region 4b is formed by carrying out ion implantation. Drain regions 3 and a source region 4 are formed by removing the photo-resist layers 31, and by carrying out ion implantation using the control gate electrodes 12 as a mask. The source region is formed by removing a part of the isolation region positioned adjacently to the source region located in a peripheral part of the control gate electrodes 12. As a result, it is possible to reduce the distance between two of the control gate electrodes positioned adjacently as well as increasing integration level of the nonvolatile memory devices.
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: February 9, 1999
    Assignee: Rohm Co., Ltd.
    Inventor: Hiroshi Oji
  • Patent number: 5451803
    Abstract: A semiconductor memory device in which source lines for connecting source regions of memory cells disposed in a direction of word lines are composed of conductive films formed on a semiconductor substrate. Gate assemblies including components such as the word lines are formed on the semiconductor substrate. Source regions are formed in self-alignment by using the gate assemblies as masks. Source contact holes are formed above the source regions, and the source lines are in contact with the source regions in the source contact holes. The source lines are composed of conductive films formed on the semiconductor substrate between the adjacent word lines on opposite sides of any of the source regions.
    Type: Grant
    Filed: April 19, 1993
    Date of Patent: September 19, 1995
    Assignee: Rohm Co., Ltd.
    Inventors: Hiroshi Oji, Kunio Iida
  • Patent number: 5420449
    Abstract: A semiconductor device having a capacitor of a large capacitance in spite of its small area, is composed of a first insulating film formed on a semiconductor substrate, a first polysilicon film, a second insulating film and a second polysilicon film which are formed in that order on the first insulating film. The second polysilicon film is connected to the semiconductor substrate by means of a metal film to function as one electrode while the first polysilicon film functions as the other electrode. The first and second insulating film are each made of a dielectric material.
    Type: Grant
    Filed: April 13, 1994
    Date of Patent: May 30, 1995
    Assignee: Rohm Co., Ltd.
    Inventor: Hiroshi Oji
  • Patent number: 5403764
    Abstract: In a method for producing a semiconductor device having a nonvolatile memory capable of electrically writing, reading and erasing, and a read only memory; the improvement wherein the method includes a step of writing a state of "0" or "1" in the read only memory by doping said read only memory with an impurity for adjusting a threshold voltage of the read only memory, and steps for producing the read only memory other than the step of writing are the same as steps for producing the nonvolatile memory.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: April 4, 1995
    Assignee: Rohm Co., Ltd.
    Inventors: Hiroki Yamamoto, Hiroshi Oji