Patents by Inventor Hiroshi OMODERA

Hiroshi OMODERA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Printed wiring board and method for manufacturing same
    Patent number: 10952320
    Abstract: A printed wiring board in the present disclosure includes a core layer, a first buildup layer, a second buildup layer, and a through hole. The core layer has a conductor circuit located on a surface of an insulator. The first buildup layer containing a first resin is laminated on a surface of the core layer. The second buildup layer containing a second resin is laminated on a surface of the first buildup layer. The through hole extends through the core layer, the first buildup layer, and the second buildup layer. The first resin and the second resin are different from each other. The second buildup layer includes a plurality of filled vias filled with a conductor which are located around a circumference of an opening of the through hole.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: March 16, 2021
    Assignee: Kyocera Corporation
    Inventors: Tadashi Watanabe, Masakazu Nakamura, Hiroshi Omodera, Tomoko Oyama
  • PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING SAME
    Publication number: 20190098755
    Abstract: A printed wiring board in the present disclosure includes a core layer, a first buildup layer, a second buildup layer, and a through hole. The core layer has a conductor circuit located on a surface of an insulator. The first buildup layer containing a first resin is laminated on a surface of the core layer. The second buildup layer containing a second resin is laminated on a surface of the first buildup layer. The through hole extends through the core layer, the first buildup layer, and the second buildup layer. The first resin and the second resin are different from each other. The second buildup layer includes a plurality of filled vias filled with a conductor which are located around a circumference of an opening of the through hole.
    Type: Application
    Filed: March 23, 2017
    Publication date: March 28, 2019
    Applicant: KYOCERA Corporation
    Inventors: Tadashi WATANABE, Masakazu NAKAMURA, Hiroshi OMODERA, Tomoko OYAMA