Patents by Inventor Hiroshi Osuga

Hiroshi Osuga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11962227
    Abstract: An electric actuator of the disclosure includes a motor, a speed reduction mechanism, and a bearing fixed to a motor shaft having an eccentric axis portion. The speed reduction mechanism has: an externally toothed gear, an internally toothed gear, a facing member facing the externally toothed gear, column members protruding from one member of the facing member and the externally toothed gear toward the other member and surrounding the motor axis, and at least one tube member surrounding the column members. The other member has hole portions surrounding the motor axis. The column members are inserted into the hole portions respectively, and support the externally toothed gear to be swingable around the motor axis via an inner side surface of each of the hole portions. The at least one tube member surrounds the column members in the hole portions and is rotatable around a rotary axis passing through the hole portions.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: April 16, 2024
    Assignee: NIDEC TOSOK CORPORATION
    Inventors: Hiroshi Shirai, Kohei Osuga, Kenichi Ozawa
  • Publication number: 20150254820
    Abstract: The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.
    Type: Application
    Filed: May 21, 2015
    Publication date: September 10, 2015
    Inventors: Hiroshi Osuga, Takaaki Suzuki, Atsushi Kiuchi, Kazuhide Kawade, Hiroyuki Hamasaki
  • Patent number: 9071750
    Abstract: The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.
    Type: Grant
    Filed: October 15, 2011
    Date of Patent: June 30, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Osuga, Takaaki Suzuki, Atsushi Kiuchi, Kazuhide Kawade, Hiroyuki Hamasaki
  • Publication number: 20120105679
    Abstract: The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.
    Type: Application
    Filed: October 15, 2011
    Publication date: May 3, 2012
    Inventors: Hiroshi OSUGA, Takaaki Suzuki, Atsushi Kiuchi, Kazuhide Kawade, Hiroyuki Hamasaki
  • Patent number: 5168415
    Abstract: A motor control method for determining the temperature of a motor wherein the operation and nonoperation times of the motor are monitored, an estimated temperature is determined as a function of the monitored times and predetermined temperature rise and temperature fall characteristics of the motor, and the motor is stopped and/or an alaram signal is generated if the estimated temperature exceeds a predetermined temperature.
    Type: Grant
    Filed: September 27, 1990
    Date of Patent: December 1, 1992
    Assignee: Seikosha Co., Ltd.
    Inventor: Hiroshi Osuga