Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: An apparatus and method for a logic circuit that advantageously adapts to different operating voltages. In a preferred embodiment, a logic circuit of the present invention is implemented to drive a large capacitive load and includes a first driver, comprising a set of small, low-current drive transistors, a second driver, comprising a set of large, high-speed transistors, and an additional transistor connected between the two drivers. The additional transistor can be selectively enabled to speed up the operation of the logic circuit, and disabled to reduce the peak current of the logic circuit. The additional transistor is enabled by a voltage detection signal, which is active when the operating voltage of the chip is at a low level and inactive when the operating voltage of the chip is at a high level.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: The present invention is a method and apparatus for overdriving signals received by a sense amplifier circuit. To this end, an overdrive circuit comprising an n-channel common source switch drives the signal to be sensed for a period of time to a voltage level greater than a normal level. The period of time the signal is overdriven corresponds to the operating voltage of the sense amplifier circuit. Upon completion of the overdriving, a normalization circuit drives the signal to be sensed for a second period of time to the normal level, thereby preparing it for the next memory cycle so that the signals can be once again set to the desired precharge level.

Abstract: The present invention is a method and apparatus for overdriving signals received by a sense amplifier circuit. To this end, an overdrive circuit drives the signal to be sensed for a period of time to a voltage level greater than a normal level. The length of the period of time corresponds to the location of the sense amplifier circuit relative to a sense enabling circuit. Upon completion of the overdriving, a normalization circuit drives the signal to be sensed for a second period of time to the normal level, thereby preparing it for the next memory cycle so that the signals can be once again set to a desired precharge level.

Abstract: A circuit and method for providing a plurality of voltage regulators whose outputs are constant for ranges of different external voltages are disclosed. The voltage regulators are made to be adaptable to two different ranges of external voltages through use of a master-slice technique. Furthermore, in a first voltage regulator, the supply current capability of the regulator is significantly increased under very low external voltage conditions. In a second voltage regulator, the voltage level on any node of the regulator does not exceed a voltage level that is too high, yet still sinks most of its current from the external power supply. A third voltage regulator is able to charge and discharge its output voltage so that it will maintain at a constant level. Finally, a fourth voltage regulator is optimized to reduce dielectric leakage.

Abstract: The present invention is a method and apparatus for reducing the peak current for all the bit mats during a CAS-before-RAs refresh operation of a DRAM. To this end, a circuit is created to detect a CAS-before-RAS refresh operation. When a CBR refresh is detected, the amplifying of the bit mats are offset from each other, thereby staggering the time when each bit mat draws its peak current. In an alternative embodiment, when a CBR refresh is detected, the activation of the word lines are offset from each other, thereby staggering the time when each bit mat draws its peak current.

Abstract: A method of fabricating a semiconductor integrated circuit device includes: recessing a second surface portion of a semiconductor substrate; forming elements of a first circuit region capable of performing a first function at a first surface portion of the semiconductor substrate and elements of a second circuit region capable of performing a second function at the recessed second surface portion of the semiconductor substrate, the elements of the first circuit region and those of the second circuit region having relatively small and large sizes as generally measured in a direction perpendicular to the surface portions of the semiconductor substrate, respectively; forming an insulating film to cover the first and second circuit regions, with a result that a level difference is caused between first and second portions of the insulating film on the first and second circuit regions at a relatively lower level and at a relatively higher level, respectively; effecting chemical-mechanical planarization of the insul

Abstract: A dynamic RAM is provided using a sense amplifier compensating for the disparities of characteristics for paired MOSFET's. With this arrangement parasitic capacitance of the bit lines can be increased to be at least 20 times the capacitance of the memory cells. Each bit line is bisected by a switch MOSFET and is disconnected thereby as needed. A plurality of sets of memory arrays are furnished, each including a switch MOSFET for interconnecting common source lines to which the sense amplifier is connected. This permits recycling of the charges of the common source lines.