Patents by Inventor Hiroshi Sakuraba
Hiroshi Sakuraba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7387935Abstract: A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a partType: GrantFiled: September 14, 2004Date of Patent: June 17, 2008Assignees: Sharp Kabushiki KaishaInventors: Fujio Masuoka, Hiroshi Sakuraba, Fumiyoshi Matsuoka, Syounosuke Ueno, Ryusuke Matsuyama, Shinji Horii, Takuji Tanigami
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Patent number: 7088617Abstract: A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in theType: GrantFiled: August 16, 2004Date of Patent: August 8, 2006Assignees: Sharp Kabushiki Kaisha, Fujio MasuokaInventors: Fujio Masuoka, Hiroshi Sakuraba, Fumiyoshi Matsuoka, Syounosuke Ueno, Ryusuke Matsuyama, Shinji Horii
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Patent number: 7009888Abstract: A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage toType: GrantFiled: July 8, 2004Date of Patent: March 7, 2006Assignee: Sharp Kabushiki KaishaInventors: Fujio Masuoka, Hiroshi Sakuraba, Fumiyoshi Matsuoka, Syounosuke Ueno, Ryusuke Matsuyama, Shinji Horii
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Publication number: 20050063237Abstract: A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a partType: ApplicationFiled: September 14, 2004Publication date: March 24, 2005Applicants: Fujio MASUOKA, SHARP KABUSHIKI KAISHAInventors: Fujio Masuoka, Hiroshi Sakuraba, Fumiyoshi Matsuoka, Syounosuke Ueno, Ryusuke Matsuyama, Shinji Horii, Takuji Tanigami
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Publication number: 20050051806Abstract: A memory cell unit including: a semiconductor substrate having a source diffusion layer provided in a surface thereof; a column-shaped semiconductor layer provided on the source diffusion layer and having a drain diffusion layer provided in an uppermost portion thereof; a memory cell arrangement which includes a plurality of memory cells arranged in series with the intervention of a first impurity diffusion layer; a first selection transistor connected to one end of the memory cell arrangement with the intervention of a second impurity diffusion layer and connected to the drain diffusion layer; and a second selection transistor connected to the other end of the memory cell arrangement with the intervention of a third impurity diffusion layer and connected to the source diffusion layer; wherein a distance between the third impurity diffusion layer and the source diffusion layer is greater than a distance between impurity diffusion layers disposed on opposite sides of each of the memory cells, whereby punch-thrType: ApplicationFiled: August 30, 2004Publication date: March 10, 2005Applicants: FUJIO MASUOKA, SHARP KABUSHIKI KAISHAInventors: Fujio Masuoka, Hiroshi Sakuraba, Fumiyoshi Matsuoka, Syounosuke Ueno
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Publication number: 20050047209Abstract: A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in theType: ApplicationFiled: August 16, 2004Publication date: March 3, 2005Applicants: Fujio Masuoka, SHARP KABUSHIKI KAISHAInventors: Fujio Masuoka, Hiroshi Sakuraba, Fumiyoshi Matsuoka, Syounosuke Ueno, Ryusuke Matsuyama, Shinji Horii
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Publication number: 20050012134Abstract: A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage toType: ApplicationFiled: July 8, 2004Publication date: January 20, 2005Applicants: Fujio Masuoka, SHARP KABUSHIKI KAISHAInventors: Fujio Masuoka, Hiroshi Sakuraba, Fumiyoshi Matsuoka, Syounosuke Ueno, Ryusuke Matsuyama, Shinji Horii
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Publication number: 20040262681Abstract: A semiconductor device including: a silicon pillar having a high-resistivity region and first and second highly doped regions sandwiching the high-resistivity region therebetween, the high-resistivity region having an impurity concentration of 1017 cm−3 or less; an insulator surrounding the high-resistivity region; and a conductor surrounding the insulator, wherein the conductor is made of a material which permits a voltage applied to the conductor to control an electric current flowing between the first and second highly doped regions and which has a work function bringing the high-resistivity region to a perfect depletion condition during the flow of the electric current between the first and second highly doped regions.Type: ApplicationFiled: May 25, 2004Publication date: December 30, 2004Applicants: FUJIO MASUOKA, SHARP KABUSHIKI KAISHAInventors: Fujio Masuoka, Hiroshi Sakuraba, Yasue Yamamoto