Abstract: A semiconductor integrated circuit that operates on multiple supply potentials including a first potential and a second potential that is higher than the first potential. The semiconductor integrated circuit includes a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor that lowers the second supply potential applied to a gate thereof to output a lowered potential from a source thereof, a judging circuit operating on the potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level, and a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit.

Abstract: To provide a switch that can hold a switch knob at neutral and prevent play while reducing a number of parts. In the switch, an operating lever portion of a switch knob is inserted from an opening of a knob attaching portion provided at a switch case and the switching knob is axially supported by the knob attaching portion to be capable of operating to pivot, wherein an elastic pin portion is integrally provided to the switch knob, an engaging hole for engaging the elastic pin portion is provided to a side of the switch case, and when the switch knob is operated to pivot, the switch knob is urged to a neutral portion relative to the knob attaching portion by elastic force by deforming the elastic pin portion to the engaging hole.

Abstract: The invention provides an integrated circuit that permits input of a signal of a potential which is higher than a power supply voltage supplied to an interface circuit and also higher than a maximum rated voltage allowable for a gate electrode of a transistor forming an interface circuit, even in a non-access mode. The invention can include a gate voltage control circuit that produces a gate voltage to be applied to a gate electrode of a transfer gate which is connected between an external input terminal and an input end of an input buffer and transmits an external signal input from the external input terminal to the input end of the input buffer.

Abstract: A semiconductor integrated circuit is provided that handles the input/output of a signal with an external circuit. The circuit includes a transistor transmitting a signal between the external circuit and an internal circuit with a drain/source therebetween at a given gate voltage. A first gate voltage supply circuit supplies a voltage at the gate of the transistor when supplied with a first power voltage at a first level of a control signal. A second gate voltage supply circuit supplies a voltage at the gate of the transistor when supplied with a second power voltage that is lower than the first power voltage at a second level of a control signal.

Abstract: A semiconductor integrated circuit is provided that operates with a first power supply voltage and a second power supply voltage that is higher than the first power supply voltage. The circuit comprises at least one transistor that drops the second power supply voltage, a first-stage level shifter operated with a voltage supplied from the second power supply voltage via at least one transistor and shifting a level of a signal input from a circuit that is operated with the first power supply voltage, and a second-stage level shifter operated with the second power supply voltage and shifting a level of a signal input from at least one level shifter.

Abstract: A low cost automotive power window switch having few window operating switches uses a single switch to select which of the four windows to operate, and to control the window locks. The power window switch has a window operating switch 3 for raising and lowering each of the car windows, and a mode selector switch 2 for switching between the windows. The mode selector switch 2 also has a window lock switch function for locking and unlocking the windows.

Abstract: The invention provides technologies which can restrict damage due to static electricity to a gate insulating film of a transistor inside a semiconductor device forming an oscillating circuit. In particular, an oscillating circuit can include an oscillator and a semiconductor device which utilizes the oscillator. The semiconductor device can include an inverting amplifier which is provided in parallel with the oscillator and comprises an insulated gate type field effect transistor; a buffer circuit which includes an insulated gate type field effect transistor and is used to send out a signal output from the inverting amplifier to another circuit, and a transmission gate which is provided between the output terminal of the inverting amplifier and the input terminal of the buffer circuit, and includes an insulated gate type field effect transistor.

Abstract: The invention provides an integrated circuit that permits input of a signal of a potential which is higher than a power supply voltage supplied to an interface circuit and also higher than a maximum rated voltage allowable for a gate electrode of a transistor forming an interface circuit, even in a non-access mode. The invention can include a gate voltage control circuit that produces a gate voltage to be applied to a gate electrode of a transfer gate which is connected between an external input terminal and an input end of an input buffer and transmits an external signal input from the external input terminal to the input end of the input buffer.

Abstract: The invention provides a semiconductor device by which the size of an inverting amplifier being capable of intermittently outputting an oscillation signal can be downsized. The semiconductor device can be installed in parallel with an oscillator and include an inverting amplifier intermittently outputting oscillation signal in response to control signal.

Abstract: The invention provides a semiconductor device that enables examination of a wafer in an initial stage to check whether the wafer is acceptable or defective in the case of DC examinations for circuit elements and also AC examinations for circuit delay times and the like. A semiconductor device is equipped with (a) a semiconductor wafer including a plurality of chip regions in which a required circuit is formed, and a scribe region to divide the plurality of chip regions, (b) a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors, and (c) an output pad formed in the scribe region and connected to the test circuit.

Abstract: When static electricity having an excessive voltage is applied to a VSS terminal, the static electricity may be transmitted to an inner cell directly connected to a VSS cell before the static electricity is discharged to the outside via an electrostatic protection circuit, possibly resulting in electrostatic destruction. Bypasses are thus provided to bypass the static electricity applied to a VSS terminal to a higher wiring layer, which allow only excessive static electricity to be selectively discharged to the outside via an electrostatic protection circuit.

Abstract: A switch which can widen a degree of freedom of setting height and shape of a click groove while providing a click groove on a side of a movable contact and promote operation feeling without increasing cost. This switch brings a movable contact into contact with a fixed contact and separates the movable contact therefrom by pivoting a movable piece by moving a steel ball on the movable piece by operating a switch knob; wherein the movable piece is provided with a flat click portion having a contact portion and a click groove at an end edge thereof, the click portion being arranged erect relative to a housing; a steel ball contained in a ball support portion via a coil spring; and an opening of the ball support portion provided with a fitting groove to be fitted loosely to the end edge of the click portion of the movable piece.

Abstract: A semiconductor device 100 has a peripheral cell region 102 and an internal cell region. The peripheral cell region is provided with a signal input terminal 110 that inputs input signals having different voltage levels in a normal operation mode and in a test mode starting time; a first transmission circuit 120 that provides the input signal to the internal cell region; and a second transmission circuit 150 that outputs a control signal indicating a test mode when the input signal has a voltage level equivalent to a voltage to be provided when the test mode is started. Also, a control circuit 180 that cuts off current that flows in the second transmission circuit 150 when the input signal has a voltage level to be provided in the normal operation mode. The control circuit 180 includes first and second P-type transistors 182 and 184 formed in a floating N-type well.

Abstract: A semiconductor device and a test method therefor can perform delay evaluation without depending on a chip size and a measuring unit. An input I/O circuit and an output I/O circuit are disposed on a semiconductor chip of a semiconductor device. A test cell including a delay evaluation circuit is disposed in a basic cell area of the chip core portion of the semiconductor chip. The test cell includes a first delay circuit which has plural stages of inverters connected to one another only by a first interconnect layer and a delay evaluation switching circuit. The test cell can be switched between a first measurement mode for measuring a delay time between the input I/O circuit and the output I/O circuit via a through path and a second measurement mode for measuring a delay time between the input I/O circuit and the output I/O circuit via the first delay circuit.

Abstract: An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.

Abstract: To provide a switch that can hold a switch knob at neutral and prevent play while reducing a number of parts. In the switch, an operating lever portion of a switch knob is inserted from an opening of a knob attaching portion provided at a switch case and the switching knob is axially supported by the knob attaching portion to be capable of operating to pivot, wherein an elastic pin portion is integrally provided to the switch knob, an engaging hole for engaging the elastic pin portion is provided to a side of the switch case, and when the switch knob is operated to pivot, the switch knob is urged to a neutral portion relative to the knob attaching portion by elastic force by deforming the elastic pin portion to the engaging hole.

Abstract: To provide a switch which can widen a degree of freedom of setting height and shape of a click groove while providing the click groove on a side of a movable contact and promote operation feeling without increasing cost. The switch for bringing a movable contact into contact with a fixed contact and separating the movable contact therefrom by pivoting a movable piece by moving a steel ball on the movable piece by operating to pivot a switch knob, wherein the movable piece is provided with a flat click portion made of resin having a contact portion made of a conductive material and a click groove at an end edge thereof, the click portion is arranged to erect relative to a housing, a steel ball is contained in a ball support portion via a coil spring and an opening of the ball support portion is provided with a fitting groove to be fitted loosely to the end edge of the click portion of the movable piece.

Abstract: The invention provides a semiconductor device that enables examination of a wafer in an initial stage to check whether the wafer is acceptable or defective in the case of DC examinations for circuit elements and also AC examinations for circuit delay times and the like. A semiconductor device is equipped with (a) a semiconductor wafer including a plurality of chip regions in which a required circuit is formed, and a scribe region to divide the plurality of chip regions, (b) a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors, and (c) an output pad formed in the scribe region and connected to the test circuit.

Abstract: A semiconductor device is provided having an internal circuit in which input data is gated and supplied to the internal circuit according to an internal control signal generated within the semiconductor device. The semiconductor device has N number (N being two or greater integers) of data input terminals for inputting input data, and a test mode input terminal for inputting a test mode signal. An OR device is provided for obtaining a logical sum of the internal control signal and the test mode signal. The semiconductor device also has N number of gate circuits that are supplied with the input data applied to the N data input terminals, respectively. When an output of the OR device is active, those of the N gate circuits responsive to the output of the OR device pass the input data applied to the data input terminals. The internal circuit is supplied with outputs of the N gate circuits.

Abstract: A semiconductor device defines a peripheral circuit region and a central circuit region. The peripheral circuit region includes a control signal wiring extending through the peripheral circuit region, a first cell having a test terminal connecting to the control signal wiring, N number of second cells that input and/or output signals, each having a signal terminal, and a plurality of third cells, each having a power source terminal. Among N number of the second cells, n (n<N) number of the second cells have input signal wirings coupled to the signal terminals, and potential fixing circuits that fix the potential on the input signal wirings. Each of the potential fixing circuits has one of a plurality of control terminals. A plurality of serially connected buffers are coupled to the control signal wiring.