Patents by Inventor Hiroshi Shimaya
Hiroshi Shimaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10644533Abstract: An electronic device, an imaging apparatus, and a method of switching a power source that can smoothly switch a power source while preventing instantaneous interruption in a case where power source supply lines are shut off from each other between a device body and an external device on which a plurality of power sources can be mounted. A power source-switching preparation unit performs first processing for shifting an electronic device to an electric power-saving state and second processing for shifting the electronic device to a state where electric power can be supplied from a plurality of power sources, as switching preparation, and a power source-switching control unit switches a main power source according to a set order of priority in a state where the switching preparation is performed.Type: GrantFiled: May 30, 2019Date of Patent: May 5, 2020Assignee: FUJIFILM CorporationInventor: Hiroshi Shimaya
-
Publication number: 20190280516Abstract: An electronic device, an imaging apparatus, and a method of switching a power source that can smoothly switch a power source while preventing instantaneous interruption in a case where power source supply lines are shut off from each other between a device body and an external device on which a plurality of power sources can be mounted. A power source-switching preparation unit performs first processing for shifting an electronic device to an electric power-saving state and second processing for shifting the electronic device to a state where electric power can be supplied from a plurality of power sources, as switching preparation, and a power source-switching control unit switches a main power source according to a set order of priority in a state where the switching preparation is performed.Type: ApplicationFiled: May 30, 2019Publication date: September 12, 2019Applicant: FUJIFILM CorporationInventor: Hiroshi SHIMAYA
-
Patent number: 8675042Abstract: A distance to an object is measured for each of a series of left images, and the count of a distance range including the calculated distance increases. A distance range with the highest frequency of appearance is specified from the counter information of a distance table counter, and a left image in which the distance included in the specified distance range is measured is selected. The adjustment amount of the parallax amount adjusted for the selected left image and a corresponding right image is determined to be the adjustment amount of the parallax amount of a panorama image. A series of left images is combined to generate a panorama image and a series of right images is combined to generate a panorama image. A panorama image displayed in stereoscopic view is generated based on the determined adjustment amount of the parallax amount.Type: GrantFiled: March 28, 2011Date of Patent: March 18, 2014Assignee: FUJIFILM CorporationInventor: Hiroshi Shimaya
-
Publication number: 20110242273Abstract: A distance to an object is measured for each of a series of left images, and the count of a distance range including the calculated distance increases. A distance range with the highest frequency of appearance is specified from the counter information of a distance table counter, and a left image in which the distance included in the specified distance range is measured is selected. The adjustment amount of the parallax amount adjusted for the selected left image and a corresponding right image is determined to be the adjustment amount of the parallax amount of a panorama image. A series of left images is combined to generate a panorama image and a series of right images is combined to generate a panorama image. A panorama image displayed in stereoscopic view is generated based on the determined adjustment amount of the parallax amount.Type: ApplicationFiled: March 28, 2011Publication date: October 6, 2011Applicant: FUJIFILM CORPORATIONInventor: Hiroshi SHIMAYA
-
Patent number: 7514960Abstract: A level shifter circuit has first to fourth transistors and a resistive element. The first transistor is activated in response to a logic signal whose high level voltage is a first voltage. The second transistor is activated in response to the inverse logic signal. Each of the first and second transistors is connected between a power supply line for supplying a second voltage and a ground line. The third transistor is connected to a drain of the first transistor through a first node. The fourth transistor is connected to a drain of the second transistor through a second node. A gate of the third transistor is connected to the drain of the second transistor through the second node. A gate of the fourth transistor is connected to the drain of the first transistor through the first node. The resistive element is connected between the first node and the second node.Type: GrantFiled: April 3, 2006Date of Patent: April 7, 2009Assignee: NEC Electronics CorporationInventor: Hiroshi Shimaya
-
Publication number: 20080238949Abstract: An electronic device including a display section, a control section, a detection section, a storage section, an acquiring section and a setting section is provided. The control section controls images corresponding to plural predetermined scenes to be displayed on the display section in predetermined order. The detection section detects an instruction input to the electronic device by a user. The storage section stores the images of the scenes, and stores setting information corresponding to the scenes in association with the scenes. The acquisition section acquires, from the storage section, setting information corresponding to the scene displayed when the instruction input from the user is detected while display of the images corresponding to the plural scenes being effected. The setting section sets the acquired setting information in the electronic device.Type: ApplicationFiled: March 17, 2008Publication date: October 2, 2008Inventor: Hiroshi SHIMAYA
-
Patent number: 7420495Abstract: An object of the present invention is to form a highly accurate current source for D/A converters. Letters from a1 to an where n is at least 4 represent current source cells that output constant currents, each of which is composed of MOS transistors etc. These current source cells are arranged in two dimensional matrix and a plurality of these current source cells are connected to form a current source that has a predetermined current value. Current source cells in any one row of the two dimensional matrix are labeled with letters from a1 to an. A first kind of row is in the same order as this row. A second kind of row is obtained from the first kind of row by exchanging a series of elements being letters from ai to ai+j where both i and j are integers at least 1 and i+j is an integer not more than n/2 with a series of elements being letters from ak to ak+j where k is an integer larger than n/2 and k+j is an integer not more than n. The two dimensional matrix comprises a same number of these two kinds of row.Type: GrantFiled: December 6, 2006Date of Patent: September 2, 2008Assignee: NEC Electronics CorporationInventor: Hiroshi Shimaya
-
Publication number: 20070126617Abstract: An object of the present invention is to form a highly accurate current source for D/A converters. Letters from a1 to an where n is at least 4 represent current source cells that output constant currents, each of which is composed of MOS transistors etc. These current source cells are arranged in two dimensional matrix and a plurality of these current source cells are connected to form a current source that has a predetermined current value. Current source cells in any one row of the two dimensional matrix are labeled with letters from a1 to an. A first kind of row is in the same order as this row. A second kind of row is obtained from the first kind of row by exchanging a series of elements being letters from ai to ai+j where both i and j are integers at least 1 and i+j is an integer not more than n/2 with a series of elements being letters from ak to ak+j where k is an integer larger than n/2 and k+j is an integer not more than n. The two dimensional matrix comprises a same number of these two kinds of row.Type: ApplicationFiled: December 6, 2006Publication date: June 7, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Hiroshi Shimaya
-
Patent number: 7173660Abstract: For an image to be displayed on a liquid crystal display, a thinning process is executed to reduce a number of pixels constructing the image. An original image of an information image is produced in accordance with a pixel number of a taken subject image. A low-pass-filter process is executed for the original image. After the low-pass-filter process, the processed original image is written in a data ROM as the information image. When a digital camera is operated, the information image is displayed on a screen of the liquid crystal display by using the data of the information image stored in the data ROM.Type: GrantFiled: September 19, 2001Date of Patent: February 6, 2007Assignee: Fuji Photo Film Co., Ltd.Inventors: Shigeo Toji, Hiroshi Shimaya
-
Publication number: 20060226875Abstract: A level shifter circuit has first to fourth transistors and a resistive element. The first transistor is activated in response to a logic signal whose high level voltage is a first voltage. The second transistor is activated in response to the inverse logic signal. Each of the first and second transistors is connected between a power supply line for supplying a second voltage and a ground line. The third transistor is connected to a drain of the first transistor through a first node. The fourth transistor is connected to a drain of the second transistor through a second node. A gate of the third transistor is connected to the drain of the second transistor through the second node. A gate of the fourth transistor is connected to the drain of the first transistor through the first node. The resistive element is connected between the first node and the second node.Type: ApplicationFiled: April 3, 2006Publication date: October 12, 2006Applicant: NEC ELECTRONICS CORPORATIONInventor: Hiroshi Shimaya
-
Publication number: 20020033895Abstract: For an image to be displayed on a liquid crystal display, a thinning process is executed to reduce a number of pixels constructing the image. An original image of an information image is produced in accordance with a pixel number of a taken subject image. A low-pass-filter process is executed for the original image. After the low-pass-filter process, the processed original image is written in a data ROM as the information image. When a digital camera is operated, the information image is displayed on a screen of the liquid crystal display by using the data of the information image stored in the data ROM.Type: ApplicationFiled: September 19, 2001Publication date: March 21, 2002Inventors: Shigeo Toji, Hiroshi Shimaya
-
Patent number: 5757430Abstract: In order to make it possible to see both a film accommodated in a film carrier and a film accommodated in a sheath, a carrier holder is rotatably provided in the upper portion of a viewer main body containing an imaging optical system, a CCD and a signal processing circuit, a carrier inlet is formed in the carrier holder, and head covers are mounted on the carrier holder so as to be capable of being opened and closed. The head covers are provided with a lighting lamp. Supporting arms are mounted on both sides of the viewer main body so as to be capable of being opened and closed.Type: GrantFiled: June 10, 1994Date of Patent: May 26, 1998Assignee: Fuji Photo Film Co., Ltd.Inventors: Yutaka Maeda, Hiroshi Shimaya, Atsushi Misawa, Shigeru Kondo
-
Patent number: 5579049Abstract: An object of the present invention is to bring a video signal obtained by imaging into a proper level without use of a controllable diaphragm. An imaging apparatus is provided with no controllable diaphragm. Peak detection is performed by a peak detecting circuit for each vertical scanning interval. A peak value is applied to a control device. Necessary shutter speed control in a shutter control circuit, gain control in a pre-amplifier circuit and gain control in a GCA are carried out. Consequently, the level of the video signal obtained by the imaging is adjusted to a proper level without controlling a diaphragm, to obtain an image of proper brightness.Type: GrantFiled: December 22, 1993Date of Patent: November 26, 1996Assignee: Fuji Photo Film Co., Ltd.Inventors: Hiroshi Shimaya, Yutaka Maeda, Chiaki Ichikawa, Toshio Nakajima
-
Patent number: 5262868Abstract: A memory card has a volatile semiconductor memory for storing therein image data, a built-in battery as a backup power for preserving the image data in the volatile semiconductor memory, and a non-volatile memory for storing therein data related to an alarm of a decrease in a voltage of the built-in battery. When the memory card is loaded on the digital, electronic, still camera, the data concerning the alarm state is read from the loaded memory card and the voltage value of the battery is sensed. If the value of the battery voltage thus determined is less than a threshold voltage attained from the data read from the memory card, an alarm is notified.Type: GrantFiled: January 13, 1992Date of Patent: November 16, 1993Assignee: Fuji Photo Film Co., Ltd.Inventors: Kiyotaka Kaneko, Hiroshi Shimaya, Izumi Miyake
-
Patent number: 5212797Abstract: A multiple-CPU system including a main CPU and at least one subordinate CPU connected thereto. Both the main and subordinate CPU are provided with a respective voltage detector circuit for detecting when a main or primary power supply voltage for the CPU's has dropped below a predetermined threshold level. When the respective detector circuit outputs a signal indicating detection of the drop in main power supply voltage, the respective CPU is placed in a standby state. However, the threshold level of the detector circuit of the main CPU is set to a voltage lower than the threshold level of the detector circuit of the subordinate CPU. As a result, the subordinate CPU is placed in a standby state before the main CPU. The main CPU is equipped with an auxiliary power supply so that when the subordinate CPU is placed in a standby state, automatic recovery is thereafter carried out by the main CPU.Type: GrantFiled: January 28, 1992Date of Patent: May 18, 1993Assignee: Fuji Photo Film Co., Ltd.Inventors: Izumi Miyake, Kiyotaka Kaneko, Yoshio Nakane, Yutaka Maeda, Hiroshi Shimaya
-
Patent number: 5210568Abstract: In a camera having a power source shared between a charging circuit for a strobe emission and a camera function section other than the charging circuit, the charging operation is inhibited during an operation of the camera function section and a battery check is inhibited during the charging operation. As a result, a runaway of a CPU of the camera due to the voltage reduction of the power source in the charging operation is avoided; moreover, inhibition of a shooting operation due to the battery check is prevented, thereby efficiently utilizing the battery capacity.Type: GrantFiled: July 20, 1992Date of Patent: May 11, 1993Assignee: Fuji Photo Film Co., Ltd.Inventors: Izumi Miyake, Kiyotaka Kaneko, Hiroshi Shimaya, Masanaga Yamamoto, Masanori Yoshida
-
Patent number: 5204601Abstract: A motor speed controller implements a speed control to phase control switch over. When the switch over occurs on initial offset between the reference speed signal phase and the current motor position phase is determined. The reference speed signal is then offset by this phase difference thereby achieving a quicker servo lock.Type: GrantFiled: November 29, 1990Date of Patent: April 20, 1993Assignee: Fuji Photo Film Co., Ltd.Inventors: Masafumi Hirata, Hiroshi Shimaya
-
Patent number: 5189570Abstract: A magnetic head advancing apparatus which advances a magnetic head to be brought into contact with a magnetic recording medium (head loading) in response to a latch-type solenoid when a power supply switch is closed. The magnetic head is separated from the magnetic recording medium (head unloading) in response to a latch-type solenoid when the power supply switch is opened, when the power supply voltage drops below a predetermined level, or when the power supply (a battery) is ejected from the apparatus. This makes it possible to prevent local permanent deformation of a magnetic disk caused by prolonged abutting contact between the magnetic head and the magnetic disk.Type: GrantFiled: August 15, 1991Date of Patent: February 23, 1993Assignee: Fuji Photo Film Co, Ltd.Inventors: Yutaka Maeda, Kiyotaka Kaneko, Izumi Miyake, Yoshio Nakane, Hiroshi Shimaya
-
Patent number: 5121218Abstract: A recording/playback apparatus is provided with a plurality of controllers (inclusive of CPU's) which, by communicating with one another, share control of each of the components of the recording/playback apparatus or of the entire apparatus. Communication among the controllers is performed in the second half of one period of a signal related to the rotational reference phase of a rotating recording medium. This makes it possible for control requiring high precision to be performed in the first half of the aforementional period without being affected by high-priority interrupts which accompany communication control. Further, in order that the aforementioned communication may be carried out in the second half of the above mentioned period, message editing is performed in the first half of the same period. This enables prompt communication processing during the short time in the second half of the period without an unnecessary waste of time.Type: GrantFiled: February 24, 1989Date of Patent: June 9, 1992Assignee: Fuji Photo Film Co., Ltd.Inventors: Izumi Miyake, Kiyotaka Kaneko, Yoshio Nakane, Yutaka Maeda, Hiroshi Shimaya
-
Patent number: RE39410Abstract: A white balance adjusting device for use in a camera which photographs a field and forms a video signal representing the field. In the white balance adjusting device, while a sequential photographing is under way, updating of the color temperature data to be used for adjusting a white balance is prohibited. Therefore, the hues of main objects in the respective frames of still images photographed by the sequential photographic operation remain unchanged, thereby maintaining the homogeneity of the main objects. Also, in the white balance adjusting device, control a device is used to provide a short response time for a quick response property in a still mode and to provide a longer response time in a movie mode when compared with the still mode. As a result, the white balance can be adjusted according to the photographic modes of the camera.Type: GrantFiled: October 20, 2000Date of Patent: November 28, 2006Assignee: Fuji Photo Film Co., Ltd.Inventors: Kiyotaka Kaneko, Izumi Miyake, Kazuya Oda, Yoshio Nakane, Hiroshi Shimaya