Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array unit and an alignment mark unit. The cell array unit includes a first memory string, a second memory string and a device isolation insulating layer. The first string is provided on a major surface of a semiconductor layer. The second string is juxtaposed with the first memory string. The device isolation insulating layer partitions the first and second memory strings from each other. The mark unit juxtaposed with the array unit includes a mark unit semiconductor layer and a mark unit insulating layer. The mark unit semiconductor layer is a part of the semiconductor layer. The mark unit insulating layer is juxtaposed with the mark unit semiconductor layer. An upper surface of the mark unit semiconductor layer is included in a plane different from a plane including an upper surface of the mark unit insulating layer.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.