Patents by Inventor Hiroshi Shirota

Hiroshi Shirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220380032
    Abstract: To provide an aerial vehicle that can realize ease of operation during driving. An aerial vehicle according to the present technology includes: a vehicle body extending in a front-rear direction; a saddle section provided on an upper side of the vehicle body; a grip section provided on the front side of the saddle section in the vehicle body; and a rotary wing section which is provided in the vehicle body and which generates lift and/or thrust with respect to the vehicle body; wherein an operation section for performing operations pertaining to actions relating to ascent and/or propulsion of the vehicle body is provided in the grip section.
    Type: Application
    Filed: October 8, 2019
    Publication date: December 1, 2022
    Inventors: Yasuhiro ARAKAWA, Yutaka TAKAGI, Takafumi OBA, Takeru SHIROTA, Yuki TAKIZAWA, Hiroshi NAKANO
  • Patent number: 9350333
    Abstract: If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit 12 includes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FF1 provided in a subsequent stage of a flip-flop FF0, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FF1 and output of the flip-flop FFT. Test data tv1 and test data tv2 are input to the malfunction pre-detecting circuit 12 in an operation test mode for testing operation of the malfunction pre-detecting circuit 12. The test data tv2 is input to the delay circuit DL. The comparator CMP compares the test data tv1 and output of the flip-flop FFT in the operation test mode.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 24, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Ito, Hiroshi Shirota
  • Publication number: 20160087612
    Abstract: If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit 12 includes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FF1 provided in a subsequent stage of a flip-flop FF0, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FF1 and output of the flip-flop FFT. Test data tv1 and test data tv2 are input to the malfunction pre-detecting circuit 12 in an operation test mode for testing operation of the malfunction pre-detecting circuit 12. The test data tv2 is input to the delay circuit DL. The comparator CMP compares the test data tv1 and output of the flip-flop FFT in the operation test mode.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 24, 2016
    Inventors: Kazuyuki ITO, Hiroshi SHIROTA
  • Patent number: 9229046
    Abstract: If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit 12 includes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FF1 provided in a subsequent stage of a flip-flop FF0, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FF1 and output of the flip-flop FFT. Test data tv1 and test data tv2 are input to the malfunction pre-detecting circuit 12 in an operation test mode for testing operation of the malfunction pre-detecting circuit 12. The test data tv2 is input to the delay circuit DL. The comparator CMP compares the test data tv1 and output of the flip-flop FFT in the operation test mode.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Ito, Hiroshi Shirota
  • Publication number: 20140152334
    Abstract: If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit 12 includes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FF1 provided in a subsequent stage of a flip-flop FF0, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FF1 and output of the flip-flop FFT. Test data tv1 and test data tv2 are input to the malfunction pre-detecting circuit 12 in an operation test mode for testing operation of the malfunction pre-detecting circuit 12. The test data tv2 is input to the delay circuit DL. The comparator CMP compares the test data tv1 and output of the flip-flop FFT in the operation test mode.
    Type: Application
    Filed: November 12, 2013
    Publication date: June 5, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Kazuyuki Ito, Hiroshi Shirota
  • Publication number: 20130196987
    Abstract: The present invention provides compounds, methods for the synthesis thereof and methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis.
    Type: Application
    Filed: October 30, 2012
    Publication date: August 1, 2013
    Applicant: EISAI CO., LTD.
    Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-Andre Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
  • Patent number: 8385403
    Abstract: This invention provides a digital broadcasting receiving unit capable of achieving synchronization of time information between a base station and a receiving unit with reference clock without use of a crystal oscillator (VCXO) having a variable frequency. The crystal oscillator oscillates a clock of a predetermined fixed frequency. A variable digital dividing circuit divides a fixed frequency by a division ratio so as to change the division ratio. A system decoder detects reference time information from the base station. A reference counter generates time information of a receiving unit. A phase comparator detects a difference between reference time information and time information. A division ratio control circuit controls the change of the division ratio based on the difference. The reference counter generates time information based on a clock having a frequency obtained by dividing by the variable digital dividing circuit and feeds back time information to the phase comparator.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: February 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Shirota, Tadashi Saito, Kazuyuki Ito, Ryosuke Okuda, Masao Aramoto
  • Patent number: 8329742
    Abstract: The present invention provides methods for the use of compounds having formula (I) in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, t, X, Y, Z, and n are as defined herein.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: December 11, 2012
    Assignee: EISAI Co., Ltd.
    Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-André Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
  • Publication number: 20120007255
    Abstract: A semiconductor device having a power supply wiring and a ground wiring is provided, which can suppress the occurrence of voltage drop in part of wiring and the occurrence of migration caused by voltage drop.
    Type: Application
    Filed: June 22, 2011
    Publication date: January 12, 2012
    Inventors: Hiroshi SHIROTA, Yasunari Shigemitsu, Kazunori Hisamura
  • Publication number: 20110201569
    Abstract: Provided are methods for treating myocardial disorders comprising administering to a subject an effective amount of a compound of formula (I) or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: September 16, 2010
    Publication date: August 18, 2011
    Inventors: Heidi Ehrentraut, Hiroshi Shirota, Georg Baumgarten, Pascal Knuefermann, Rainer Meyer
  • Publication number: 20110144101
    Abstract: The present invention provides methods for the use of compounds having formula (I) in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, t, X, Y, Z, and n are as defined herein.
    Type: Application
    Filed: July 20, 2010
    Publication date: June 16, 2011
    Applicant: EISAI CO., LTD.
    Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-André Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
  • Patent number: 7915306
    Abstract: The present invention provides compositions comprising compounds having formula (I): and additionally provides methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, X, Y, Z, and n are as defined herein. In certain embodiments, the compositions are for systemic (e.g., oral) administration. In certain embodiments, methods for the treatment of various disorders including inflammatory or autoimmune disorders comprise systemically (e.g., orally) administering to a subject in need thereof a therapeutically effective amount of a compound of formula (I).
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: March 29, 2011
    Assignee: Eisai Co., Ltd.
    Inventors: Kenichi Chiba, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Ray Wood, Satoshi Yamamoto, Naoki Yoneda
  • Publication number: 20100279978
    Abstract: The invention provides methods of reducing the severity of mucositis, involving administration of a toll-like receptor 4 antagonist.
    Type: Application
    Filed: May 7, 2010
    Publication date: November 4, 2010
    Applicant: Eisai R&D Management Co., Ltd.
    Inventors: Tetsu Kawano, Seiichi Kobayashi, Minghuang Zhang, Hiroshi Shirota
  • Patent number: 7799827
    Abstract: The present invention provides compounds having formula (I): and additionally provides methods for the synthesis thereof and methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, X, Y, Z, and n are as defined herein.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: September 21, 2010
    Assignee: Eisai Co., Ltd.
    Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-André Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
  • Patent number: 7727974
    Abstract: The invention provides methods of reducing the severity of mucositis, involving administration of a toll-like receptor 4 antagonist.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: June 1, 2010
    Assignee: Eisai R & D Management Co., Ltd.
    Inventors: Tetsu Kawano, Seiichi Kobayashi, Minghuang Zhang, Hiroshi Shirota
  • Publication number: 20080096841
    Abstract: The invention provides methods of treating and preventing heat shock protein-associated diseases and conditions.
    Type: Application
    Filed: December 17, 2007
    Publication date: April 24, 2008
    Applicant: Eisai R&D Management Co. Ltd.
    Inventors: Seiichi Kobayashi, Minghuang Zhang, Hiroshi Shirota
  • Publication number: 20080091869
    Abstract: A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of input data, and outputs a write counter value. The memory circuit stores the input data in response to the write counter value. The read counter circuit counts a read clock signal when a decision is made that the memory circuit includes data that has not yet been read out, and outputs a read counter value. The read selector circuit reads data from the memory circuit in response to the read counter value. A small scale FIFO circuit can be obtained.
    Type: Application
    Filed: November 30, 2007
    Publication date: April 17, 2008
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Hiroshi SHIROTA
  • Patent number: 7353356
    Abstract: A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of input data, and outputs a write counter value. The memory circuit stores the input data in response to the write counter value. The read counter circuit counts a read clock signal when a decision is made that the memory circuit includes data that has not yet been read out, and outputs a read counter value. The read selector circuit reads data from the memory circuit in response to the read counter value. A small scale FIFO circuit can be obtained.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: April 1, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Hiroshi Shirota
  • Publication number: 20070253493
    Abstract: This invention provides a digital broadcasting receiving unit capable of achieving synchronization of time information between a base station and a receiving unit with reference clock without use of a crystal oscillator (VCXO) having a variable frequency. The crystal oscillator oscillates a clock of a predetermined fixed frequency. A variable digital dividing circuit divides a fixed frequency by a division ratio so as to change the division ratio. A system decoder detects reference time information from the base station. A reference counter generates time information of a receiving unit. A phase comparator detects a difference between reference time information and time information. A division ratio control circuit controls the change of the division ratio based on the difference. The reference counter generates time information based on a clock having a frequency obtained by dividing by the variable digital dividing circuit and feeds back time information to the phase comparator.
    Type: Application
    Filed: April 17, 2007
    Publication date: November 1, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Hiroshi Shirota, Tadashi Saito, Kazuyuki Ito, Ryosuke Okuda, Masao Aramoto
  • Publication number: 20070072824
    Abstract: The invention provides methods of reducing the severity of mucositis, involving administration of a toll-like receptor 4 antagonist.
    Type: Application
    Filed: May 15, 2006
    Publication date: March 29, 2007
    Applicant: Eisai Co., Ltd.
    Inventors: Tetsu Kawano, Seiichi Kobayashi, Minghuang Zhang, Hiroshi Shirota