Patents by Inventor Hiroshi Shirota
Hiroshi Shirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9350333Abstract: If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit 12 includes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FF1 provided in a subsequent stage of a flip-flop FF0, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FF1 and output of the flip-flop FFT. Test data tv1 and test data tv2 are input to the malfunction pre-detecting circuit 12 in an operation test mode for testing operation of the malfunction pre-detecting circuit 12. The test data tv2 is input to the delay circuit DL. The comparator CMP compares the test data tv1 and output of the flip-flop FFT in the operation test mode.Type: GrantFiled: November 30, 2015Date of Patent: May 24, 2016Assignee: Renesas Electronics CorporationInventors: Kazuyuki Ito, Hiroshi Shirota
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Publication number: 20160087612Abstract: If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit 12 includes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FF1 provided in a subsequent stage of a flip-flop FF0, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FF1 and output of the flip-flop FFT. Test data tv1 and test data tv2 are input to the malfunction pre-detecting circuit 12 in an operation test mode for testing operation of the malfunction pre-detecting circuit 12. The test data tv2 is input to the delay circuit DL. The comparator CMP compares the test data tv1 and output of the flip-flop FFT in the operation test mode.Type: ApplicationFiled: November 30, 2015Publication date: March 24, 2016Inventors: Kazuyuki ITO, Hiroshi SHIROTA
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Patent number: 9229046Abstract: If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit 12 includes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FF1 provided in a subsequent stage of a flip-flop FF0, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FF1 and output of the flip-flop FFT. Test data tv1 and test data tv2 are input to the malfunction pre-detecting circuit 12 in an operation test mode for testing operation of the malfunction pre-detecting circuit 12. The test data tv2 is input to the delay circuit DL. The comparator CMP compares the test data tv1 and output of the flip-flop FFT in the operation test mode.Type: GrantFiled: November 12, 2013Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Kazuyuki Ito, Hiroshi Shirota
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Publication number: 20140152334Abstract: If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit 12 includes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FF1 provided in a subsequent stage of a flip-flop FF0, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FF1 and output of the flip-flop FFT. Test data tv1 and test data tv2 are input to the malfunction pre-detecting circuit 12 in an operation test mode for testing operation of the malfunction pre-detecting circuit 12. The test data tv2 is input to the delay circuit DL. The comparator CMP compares the test data tv1 and output of the flip-flop FFT in the operation test mode.Type: ApplicationFiled: November 12, 2013Publication date: June 5, 2014Applicant: Renesas Electronics CorporationInventors: Kazuyuki Ito, Hiroshi Shirota
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Publication number: 20130196987Abstract: The present invention provides compounds, methods for the synthesis thereof and methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis.Type: ApplicationFiled: October 30, 2012Publication date: August 1, 2013Applicant: EISAI CO., LTD.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-Andre Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
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Patent number: 8385403Abstract: This invention provides a digital broadcasting receiving unit capable of achieving synchronization of time information between a base station and a receiving unit with reference clock without use of a crystal oscillator (VCXO) having a variable frequency. The crystal oscillator oscillates a clock of a predetermined fixed frequency. A variable digital dividing circuit divides a fixed frequency by a division ratio so as to change the division ratio. A system decoder detects reference time information from the base station. A reference counter generates time information of a receiving unit. A phase comparator detects a difference between reference time information and time information. A division ratio control circuit controls the change of the division ratio based on the difference. The reference counter generates time information based on a clock having a frequency obtained by dividing by the variable digital dividing circuit and feeds back time information to the phase comparator.Type: GrantFiled: April 17, 2007Date of Patent: February 26, 2013Assignee: Renesas Electronics CorporationInventors: Hiroshi Shirota, Tadashi Saito, Kazuyuki Ito, Ryosuke Okuda, Masao Aramoto
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Patent number: 8329742Abstract: The present invention provides methods for the use of compounds having formula (I) in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, t, X, Y, Z, and n are as defined herein.Type: GrantFiled: July 20, 2010Date of Patent: December 11, 2012Assignee: EISAI Co., Ltd.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-André Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
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Publication number: 20120007255Abstract: A semiconductor device having a power supply wiring and a ground wiring is provided, which can suppress the occurrence of voltage drop in part of wiring and the occurrence of migration caused by voltage drop.Type: ApplicationFiled: June 22, 2011Publication date: January 12, 2012Inventors: Hiroshi SHIROTA, Yasunari Shigemitsu, Kazunori Hisamura
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Publication number: 20110201569Abstract: Provided are methods for treating myocardial disorders comprising administering to a subject an effective amount of a compound of formula (I) or a pharmaceutically acceptable salt thereof.Type: ApplicationFiled: September 16, 2010Publication date: August 18, 2011Inventors: Heidi Ehrentraut, Hiroshi Shirota, Georg Baumgarten, Pascal Knuefermann, Rainer Meyer
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Publication number: 20110144101Abstract: The present invention provides methods for the use of compounds having formula (I) in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, t, X, Y, Z, and n are as defined herein.Type: ApplicationFiled: July 20, 2010Publication date: June 16, 2011Applicant: EISAI CO., LTD.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-André Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
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Patent number: 7915306Abstract: The present invention provides compositions comprising compounds having formula (I): and additionally provides methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, X, Y, Z, and n are as defined herein. In certain embodiments, the compositions are for systemic (e.g., oral) administration. In certain embodiments, methods for the treatment of various disorders including inflammatory or autoimmune disorders comprise systemically (e.g., orally) administering to a subject in need thereof a therapeutically effective amount of a compound of formula (I).Type: GrantFiled: September 9, 2003Date of Patent: March 29, 2011Assignee: Eisai Co., Ltd.Inventors: Kenichi Chiba, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Ray Wood, Satoshi Yamamoto, Naoki Yoneda
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Publication number: 20100279978Abstract: The invention provides methods of reducing the severity of mucositis, involving administration of a toll-like receptor 4 antagonist.Type: ApplicationFiled: May 7, 2010Publication date: November 4, 2010Applicant: Eisai R&D Management Co., Ltd.Inventors: Tetsu Kawano, Seiichi Kobayashi, Minghuang Zhang, Hiroshi Shirota
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Patent number: 7799827Abstract: The present invention provides compounds having formula (I): and additionally provides methods for the synthesis thereof and methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, X, Y, Z, and n are as defined herein.Type: GrantFiled: March 7, 2003Date of Patent: September 21, 2010Assignee: Eisai Co., Ltd.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-André Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
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Patent number: 7727974Abstract: The invention provides methods of reducing the severity of mucositis, involving administration of a toll-like receptor 4 antagonist.Type: GrantFiled: May 15, 2006Date of Patent: June 1, 2010Assignee: Eisai R & D Management Co., Ltd.Inventors: Tetsu Kawano, Seiichi Kobayashi, Minghuang Zhang, Hiroshi Shirota
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Publication number: 20080096841Abstract: The invention provides methods of treating and preventing heat shock protein-associated diseases and conditions.Type: ApplicationFiled: December 17, 2007Publication date: April 24, 2008Applicant: Eisai R&D Management Co. Ltd.Inventors: Seiichi Kobayashi, Minghuang Zhang, Hiroshi Shirota
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Publication number: 20080091869Abstract: A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of input data, and outputs a write counter value. The memory circuit stores the input data in response to the write counter value. The read counter circuit counts a read clock signal when a decision is made that the memory circuit includes data that has not yet been read out, and outputs a read counter value. The read selector circuit reads data from the memory circuit in response to the read counter value. A small scale FIFO circuit can be obtained.Type: ApplicationFiled: November 30, 2007Publication date: April 17, 2008Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Hiroshi SHIROTA
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Patent number: 7353356Abstract: A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of input data, and outputs a write counter value. The memory circuit stores the input data in response to the write counter value. The read counter circuit counts a read clock signal when a decision is made that the memory circuit includes data that has not yet been read out, and outputs a read counter value. The read selector circuit reads data from the memory circuit in response to the read counter value. A small scale FIFO circuit can be obtained.Type: GrantFiled: August 19, 2002Date of Patent: April 1, 2008Assignee: Renesas Technology Corp.Inventor: Hiroshi Shirota
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Publication number: 20070253493Abstract: This invention provides a digital broadcasting receiving unit capable of achieving synchronization of time information between a base station and a receiving unit with reference clock without use of a crystal oscillator (VCXO) having a variable frequency. The crystal oscillator oscillates a clock of a predetermined fixed frequency. A variable digital dividing circuit divides a fixed frequency by a division ratio so as to change the division ratio. A system decoder detects reference time information from the base station. A reference counter generates time information of a receiving unit. A phase comparator detects a difference between reference time information and time information. A division ratio control circuit controls the change of the division ratio based on the difference. The reference counter generates time information based on a clock having a frequency obtained by dividing by the variable digital dividing circuit and feeds back time information to the phase comparator.Type: ApplicationFiled: April 17, 2007Publication date: November 1, 2007Applicant: Renesas Technology Corp.Inventors: Hiroshi Shirota, Tadashi Saito, Kazuyuki Ito, Ryosuke Okuda, Masao Aramoto
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Publication number: 20070072824Abstract: The invention provides methods of reducing the severity of mucositis, involving administration of a toll-like receptor 4 antagonist.Type: ApplicationFiled: May 15, 2006Publication date: March 29, 2007Applicant: Eisai Co., Ltd.Inventors: Tetsu Kawano, Seiichi Kobayashi, Minghuang Zhang, Hiroshi Shirota
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Publication number: 20060247448Abstract: The present invention provides compounds having formula (I): and additionally provides methods for the synthesis thereof and methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, X, Y, Z, and n are as defined herein.Type: ApplicationFiled: March 7, 2003Publication date: November 2, 2006Applicant: Eisai Co., Ltd.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmanage, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-Andre Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John Wang, Satoshi Yamamoto, Naoki Yoneda