Patents by Inventor Hiroshi Suehiro

Hiroshi Suehiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4571573
    Abstract: An apparatus for converting an analog input signal to a binary output signal, particularly for use in a facsimile system. The apparatus includes a reference level generator having its input terminal supplied with the analog input signal, a signal dividing circuitry connected between the input and output terminals of the reference level generator, an integrator having one end connected with the dividing output terminal of the signal dividing circuitry and the other end connected with a common potential level point in the apparatus and a comparator having one input terminal connected with the signal dividing output terminal of the dividing circuitry and the other input terminal connected with the input terminal of the reference level generator. The reference level on the basis of which the analog input signal is converted to a binary signal is thus adjusted for satisfactory conversion of the signal.
    Type: Grant
    Filed: October 21, 1982
    Date of Patent: February 18, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Masaharu Tadauchi, Kunio Sato, Kiyohiko Tanno, Hiroshi Suehiro, Yasuo Inoue
  • Patent number: 4543644
    Abstract: A control circuit is used for matrix drive recording. It includes a microprocessor, a RAM for storing data to be recorded therein, an address signal editing circuit for modifying the input addresses to the RAM, a shift register for converting the data from parallel to serial form and transferring it to a recording circuit, and a DMA controller for reading the data from the RAM and transferring it to the shift register.
    Type: Grant
    Filed: September 9, 1982
    Date of Patent: September 24, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Yasuyuki Kozima, Kunio Sato, Masaharu Tadauchi, Hiroshi Suehiro, Yasuo Inoue
  • Patent number: 4133043
    Abstract: A shift register type memory having major and minor loops, wherein the number of bits of the major loop is large enough to permit data of at least two blocks to simultaneously exist in the major loop when one block is constituted of data of bits the number of which is equal to the number of the minor loops, and wherein before a particular block having been transferred out from the minor loops to the major loop is again transferred in to the minor loops after travelling round the major loop, the next block is transferred out from the minor loops to the major loop.
    Type: Grant
    Filed: November 21, 1977
    Date of Patent: January 2, 1979
    Assignees: Hitachi, Ltd., Nippon Telegraph and Telephone Public Corporation
    Inventors: Minoru Hiroshima, Shigeru Yoshizawa, Nobuo Saito, Atsushi Asano, Hiroshi Suehiro, Minoru Saitoh, Keisuke Mise