Patents by Inventor Hiroshi Suenaga

Hiroshi Suenaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8548070
    Abstract: In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: October 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Shinichiro Nishioka, Yoshihide Komatsu, Hiroshi Suenaga, Kohei Masuda
  • Publication number: 20130251017
    Abstract: A comparator circuit compares a test pattern generated by a test pattern generator circuit, with a test pattern transmitted to a memory card and returned from the memory card. A control circuit determines a bandwidth corresponding to frequency components correctly transmitted between a host apparatus and the memory card, based on the returned test pattern, and selects an encoding method requiring a maximum available bandwidth. The control circuit generates a notification message indicating the selected encoding method, and encodes the notification message using the selected encoding method, and transmit the encoded notification message to the memory card. The control circuit establishes communication between the host apparatus and the memory card, when receiving a response message including an acknowledgement to the notification message, from the memory card.
    Type: Application
    Filed: May 17, 2013
    Publication date: September 26, 2013
    Applicant: Panasonic Corporation
    Inventors: Hiroshi SUENAGA, Kohei MASUDA, Hiroshi TANAKA, Tsuyoshi IKUSHIMA, Takeshi NAKAYAMA
  • Patent number: 8520563
    Abstract: A host device and a slave device are set to a full-duplex mode by temporarily switching the communication direction of a first transmission channel or a second transmission channel after completing transmission and reception of a predetermined number of data packets in the half-duplex mode. The host device or the slave device can thus transmit an interrupt request, such as a request associated with a wait status or a busy status, to its communication target using the temporary full-duplex mode. This enables the host device or the slave device to process such an interrupt request during high-speed data transfer performed in the half-duplex mode.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: August 27, 2013
    Assignee: Panasonic Corporation
    Inventors: Tadashi Ono, Isao Kato, Hideyuki Yamada, Shinichiro Nishioka, Hiroshi Suenaga, Tsutomu Sekibe
  • Publication number: 20130114657
    Abstract: A signal transmission device including: a differential signal transmission unit having two output terminals for outputting a differential signal to a paired signal lines including first and second signal lines; a single-ended signal transmission unit having two output terminals for outputting independent two-channel single-ended signals to the paired signal lines; and a filter unit having first and second common mode filters. One terminal of the differential signal transmission unit and one terminal of the single-ended signal transmission unit are connected to the first signal line via one inductor of the first common mode filter of the filter unit. The other one terminal of the differential signal transmission unit and the other one terminal of the single-ended signal transmission unit are connected to the second signal line via one inductor of the second common mode filter of the filter unit.
    Type: Application
    Filed: February 13, 2012
    Publication date: May 9, 2013
    Inventors: Osamu Shibata, Hiroshi Suenaga
  • Publication number: 20130045635
    Abstract: A high-speed interface connector is used for connecting a cable or a memory card each having a differential transmission system signal pin arrangement including a pair of differential transmission signaling pins that are adjacent to each other and two stable potential pins provided on both sides of the pair of differential transmission signaling pins, the two stable potential pins having potentials different from each other. The connector includes: a first and a second contact terminals for differential transmission respectively connected to the pair of differential transmission signaling pins; and a third and a fourth contact terminals provided on both sides of the first and the second contact terminal, the third contact terminal adjacent to the first contact terminal being connected to one of the two stable potential pins, and the fourth contact terminal adjacent to the second contact terminal having a potential identical to that of the third contact terminal.
    Type: Application
    Filed: February 3, 2012
    Publication date: February 21, 2013
    Inventors: Hiroshi Suenaga, Yutaka Nakamura, Yukihiro Fukumoto
  • Patent number: 8351356
    Abstract: A data communication system for starting transmission and reception of target data for processing upon recognition that switching between communication modes is completed. The data communication system includes a master communication device and a slave communication device that continuously perform, at a time of switching from half-duplex communication to full-duplex communication, (i) a handshake using a directional control code indicating the switching and a preamble code indicating completion of the switching and (ii) a handshake using the preamble code and an acknowledge code indicating receipt of the preamble code, whereby each of the devices recognizes that the switching between communication modes by the opposite device is completed and starts transmission and reception of the target data.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: January 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Shinichiro Nishioka, Hiroshi Suenaga, Tsutomu Sekibe, Isao Kato, Tadashi Ono, Hideyuki Yamada
  • Publication number: 20120112784
    Abstract: An IC package includes an integrated circuit for transmitting and receiving a pair of differential signals composed of a signal having positive polarity and a signal having negative polarity, a first signal terminal for transmitting the signal having positive polarity, a second signal terminal for transmitting the signal having negative polarity, and a third terminal arranged between the first signal terminal and the second signal terminal. The first and second terminals are electrically connected to the integrated circuit, and the third terminal is not electrically connected to the integrated circuit.
    Type: Application
    Filed: April 13, 2011
    Publication date: May 10, 2012
    Inventors: Kohei Masuda, Osamu Shibata, Hiroshi Suenaga, Yoshiyuki Saito
  • Publication number: 20120021640
    Abstract: A serial-parallel conversion circuit provided on one end of a cable body converts a first serial signal into parallel signals and outputs the parallel signals to parallel signal lines. A parallel-serial conversion circuit provided on another end of the cable body converts the parallel signals inputted from the parallel signal lines into a second serial signal and outputs the second serial signal to outside.
    Type: Application
    Filed: April 26, 2010
    Publication date: January 26, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Kohei Masuda, Hiroshi Suenaga, Osamu Shibata, Yoshiyuki Saito
  • Patent number: 8099537
    Abstract: It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: January 17, 2012
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Suenaga, Osamu Shibata, Yoshiyuki Saito, Toru Iwata, Noriaki Takeda, Takaharu Yoshida
  • Publication number: 20110280322
    Abstract: A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.
    Type: Application
    Filed: October 13, 2010
    Publication date: November 17, 2011
    Inventors: Hiroshi Suenaga, Osamu Shibata, Yoshiyuki Saito, Kohei Masuda, Yoshihide Komatsu, Masashi Suzuki
  • Publication number: 20110268198
    Abstract: In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.
    Type: Application
    Filed: November 1, 2010
    Publication date: November 3, 2011
    Inventors: Shinichiro Nishioka, Yoshihide Komatsu, Hiroshi Suenaga, Kohei Masuda
  • Publication number: 20110241432
    Abstract: To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal. A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller.
    Type: Application
    Filed: November 1, 2010
    Publication date: October 6, 2011
    Inventors: Shinichiro Nishioka, Yoshihide Komatsu, Hiroshi Suenaga, Kohei Masuda
  • Publication number: 20110182216
    Abstract: An interrupt request cannot be transmitted while a data read command or a data write command transmitted from a host device to a slave device is being processed in a half-duplex mode. Disclosed are a host device and a slave device that are set to a full-duplex mode by temporarily switching the communication direction of a first transmission channel or a second transmission channel after completing transmission and reception of a predetermined number of data packets in the half-duplex mode. The host device or the slave device can thus transmit an interrupt request, such as a request associated with a wait status or a busy status, to its communication target using the temporary full-duplex mode. This enables the host device or the slave device to process such an interrupt request during high-speed data transfer performed in the half-duplex mode.
    Type: Application
    Filed: May 29, 2009
    Publication date: July 28, 2011
    Inventors: Tadashi Ono, Isao Kato, Hideyuki Yamada, Shinichiro Nishioka, Hiroshi Suenaga, Tsutomu Sekibe
  • Patent number: 7940086
    Abstract: An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: May 10, 2011
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Suenaga, Osamu Shibata, Yoshiyuki Saito, Toru Iwata, Masayuki Toyama, Kyoko Hirata
  • Publication number: 20110103224
    Abstract: A data communication system for starting transmission and reception of target data for processing upon recognition that switching between communication modes is completed. The data communication system includes a master communication device and a slave communication device that continuously perform, at a time of switching from half-duplex communication to full-duplex communication, (i) a handshake using a directional control code indicating the switching and a preamble code indicating completion of the switching and (ii) a handshake using the preamble code and an acknowledge code indicating receipt of the preamble code, whereby each of the devices recognizes that the switching between communication modes by the opposite device is completed and starts transmission and reception of the target data.
    Type: Application
    Filed: June 11, 2009
    Publication date: May 5, 2011
    Inventors: Shinichiro Nishioka, Hiroshi Suenaga, Tsutomu Sekibe, Isao Kato, Tadashi Ono, Hideyuki Yamada
  • Patent number: 7899960
    Abstract: A card controller receives data from a recording card via a socket. A read clock is transmitted in a main transmission wiring, and the data is transmitted in a data transmission wiring. The read clock is withdrawn from the card controller by an outgoing transmission wiring and retrieved into the card controller by an incoming transmission wiring. A transmission delay amount of the outgoing transmission wiring is equal to that of the main transmission wiring, and a transmission delay amount of the incoming transmission wiring is equal to that of the data transmission wiring. The card controller receives the data in synchronization with the read clock retrieved by the incoming transmission wiring.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: March 1, 2011
    Assignee: Panasonic Corporation
    Inventors: Osamu Shibata, Hiroshi Suenaga, Yoshiyuki Saito
  • Patent number: 7886085
    Abstract: An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: February 8, 2011
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Suenaga, Osamu Shibata, Noriaki Takeda, Toru Iwata, Takaharu Yoshida, Yoshiyuki Saito
  • Patent number: 7843224
    Abstract: An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: November 30, 2010
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Suenaga, Osamu Shibata, Yoshiyuki Saito, Toru Iwata, Masayuki Toyama, Kyoko Hirata
  • Publication number: 20100289534
    Abstract: An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.
    Type: Application
    Filed: July 30, 2010
    Publication date: November 18, 2010
    Inventors: Hiroshi SUENAGA, Osamu Shibata, Yoshiyuki Saito, Toru Iwata, Masayuki Toyama, Kyoko Hirata
  • Publication number: 20090290274
    Abstract: According to the present invention, the setting height position of a first terminal is set to be lower than the setting height position of a second terminal on the terminal formation surface of a printed substrate, so that the protection of an internal circuit and the transmission of a high-speed signal can be both achieved.
    Type: Application
    Filed: May 19, 2009
    Publication date: November 26, 2009
    Inventors: Hiroshi SUENAGA, Yoshiyuki Saito, Osamu Shibata, Yukihiro Fukumoto