Abstract: A synchronizer-mechanism-equipped transmission capable of moving tips of sleeve teeth and ring teeth away from butting each other by moving a synchronizer sleeve with biasing means even if the tips of the sleeve teeth and ring teeth are in contact when actuator driving stops. When sleeve teeth of a synchronizer sleeve that moves during gear shifting are located at a first synchronization position where the sleeve teeth begin to come into contact with ring teeth, a pressing member of a detent mechanism is in contact with a pre-gear-shifting detent recessed portion of a star cam.

Abstract: A twin-clutch transmission that can always effectively reduce gear shift shock and a collision sound even under the existence of variation attributed to component tolerance and change over the ages attributed to wear. A twin-clutch transmission calculates a rotational speed difference (|Na?Nb|) between an odd-stage main shaft rotational speed (Na) and an even-stage main shaft rotational speed (Nb) and learns synchronization start gear shift drive displacement (?s) detected by a gear shift drive displacement detecting unit at the timing at which the rotational speed difference (|Na?Nb|) reaches a predetermined synchronization start determination rotational speed difference (Ds) from gear shift start. The twin-clutch transmission controls an actuator on the basis of the learned synchronization start gear shift drive displacement (?s).

Abstract: A shift drum angle detecting device for a transmission includes shift forks, a shift drum, a first sensor shaft, a first angle sensor, a speed increasing mechanism, and a second angle sensor. The first angle sensor is to detect a rotational angle of the first sensor shaft to output a first output value based on the rotational angle. The speed increasing mechanism includes a speed increasing drive member, a speed increasing driven member, and a second sensor shaft. The second angle sensor is provided to the second sensor shaft to detect a rotational angle of the second sensor shaft and to output a second output value based on the rotational angle. A rotational angle of the shift drum is to be detected based on the first output value output from the first angle sensor and the second output value output from the second angle sensor.

Abstract: A synchronizer-mechanism-equipped transmission capable of moving tips of sleeve teeth and ring teeth away from butting each other by moving a synchronizer sleeve with biasing means even if the tips of the sleeve teeth and ring teeth are in contact when actuator driving stops. When sleeve teeth of a synchronizer sleeve that moves during gear shifting are located at a first synchronization position where the sleeve teeth begin to come into contact with ring teeth, a pressing member of a detent mechanism is in contact with a pre-gear-shifting detent recessed portion of a star cam.

Abstract: A twin-clutch transmission that can always effectively reduce gear shift shock and a collision sound even under the existence of variation attributed to component tolerance and change over the ages attributed to wear. A twin-clutch transmission calculates a rotational speed difference (|Na?Nb|) between an odd-stage main shaft rotational speed (Na) and an even-stage main shaft rotational speed (Nb) and learns synchronization start gear shift drive displacement (?s) detected by a gear shift drive displacement detecting unit at the timing at which the rotational speed difference (|Na?Nb|) reaches a predetermined synchronization start determination rotational speed difference (Ds) from gear shift start. The twin-clutch transmission controls an actuator on the basis of the learned synchronization start gear shift drive displacement (?s).

Abstract: A shift drum angle detecting device for a transmission includes shift forks, a shift drum, a first sensor shaft, a first angle sensor, a speed increasing mechanism, and a second angle sensor. The first angle sensor is to detect a rotational angle of the first sensor shaft to output a first output value based on the rotational angle. The speed increasing mechanism includes a speed increasing drive member, a speed increasing driven member, and a second sensor shaft. The second angle sensor is provided to the second sensor shaft to detect a rotational angle of the second sensor shaft and to output a second output value based on the rotational angle. A rotational angle of the shift drum is to be detected based on the first output value output from the first angle sensor and the second output value output from the second angle sensor.

Abstract: A vehicle transmission wherein a single shift spindle is provided with a master arm to operate the transmission via an accumulation mechanism and a clutch lever to operate a clutch, capable of more reliably realizing disconnection of the clutch after the completion of accumulation necessary for a shift operation. A vehicle transmission includes a master arm provided on a shift spindle for transmitting a rotational force to a shift drum of a transmission to rotate and operate the shift drum with a clutch lever provided on the shift spindle, to operate the clutch. An accumulation mechanism is capable of accumulating the rotational force transmitted from the shift spindle to the master arm. The master arm and the clutch lever are interlocked with each other. A delay mechanism is provided that delays the clutch disconnection operation with the clutch lever before accumulation is completed between the shift spindle and the clutch.

Abstract: A vehicle transmission wherein a single shift spindle is provided with a master arm to operate the transmission via an accumulation mechanism and a clutch lever to operate a clutch, capable of more reliably realizing disconnection of the clutch after the completion of accumulation necessary for a shift operation. A vehicle transmission includes a master arm provided on a shift spindle for transmitting a rotational force to a shift drum of a transmission to rotate and operate the shift drum with a clutch lever provided on the shift spindle, to operate the clutch. An accumulation mechanism is capable of accumulating the rotational force transmitted from the shift spindle to the master arm. The master arm and the clutch lever are interlocked with each other. A delay mechanism is provided that delays the clutch disconnection operation with the clutch lever before accumulation is completed between the shift spindle and the clutch.

Abstract: A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition.

Abstract: Each optical repeater in an optical transmission system includes an optical amplifier, and a control circuit for controlling the optical transmission. Furthermore, each optical repeater transmits management information to the next optical repeater. The control circuit checks the status of the optical amplifier and obtains monitoring information. The control circuit generates management information in accordance with the monitoring information and the management information transmitted from the upstream side optical repeater. The management information is converted to an optical signal and transmitted to the next optical repeater. A receiving station receives the management information. The management information includes an ID code for an optical repeater which has failed and the status of the failure.

Abstract: A semiconductor integrated circuit has n number of operating circuits that each operate at a predetermined cycle time; n number of wirings that transmit activation signals with respect to said n number of wirings; and a selector drive circuit that sends activation signals to said n number of wirings at respectively different cycle times. By avoiding the simultaneous drive of the operation circuits, the widths of wirings are maintained.

Abstract: A cascade sense amplifier includes section separated sense amplifiers, a cascade wiring and a main sense amplifier. The main sense amplifier has a capacitance regulation element provided at a base potential of input transistors constituting a data input end. The element is comprised of a metal oxide semiconductor (MOS) transistor for forming a capacitance corresponding to a potential V.sub.SS mainly forming a capacitance by the cascade wiring. A size of the element is determined in the manner that the base potential drop time of the transistors is equal to a potential drop time of the cascade wiring when a power source voltage V.sub.CC drops. Even though the power source voltage V.sub.CC drops, the transistors have no cut-off condition so as to prevent the read-out time from delaying. Especially, if the element is comprised of a MOS transistor, it is possible to use an extremely thin gate insulation layer as a dielectric, thereby suppressing an increase of a chip size.

Abstract: A semiconductor IC device includes a memory cell group; a pair of bit lines connected to the cell group; plural equalization transistors T.sub.R connected between the bit lines; address transition detectors ATD for detecting changes in address bits; and plural equalizing pulse generating circuits composed of plural logical gates, 15 to 22, respectively and provided for each equalization transistor to generate an equalizing pulse signal to each equalization transistor so that the levels of the two bit lines can be equalized with each other. Since signals outputted from the address transition detectors are synthesized, in particular at a node to which the equalizing pulse signal is applied, the number of logical gate stages to synthesize the detector output signals can be reduced and the wire lengths (e.g. wire capacitances) of the logical gates can be well balanced, thus improving the equalizing speed of the IC device.

Abstract: A semiconductor IC device including a main circuit block and at least one subcircuit block, each having a ground terminal, a supply voltage terminal and an input or output terminal. A first ground line is connected to the ground terminal of the main circuit block and arranged within a wiring domain of the main circuit block and adjacent to the subcircuit blocks. A second ground line is connected to the ground terminal of the subcircuit block and arranged within a wiring domain of the subcircuit block and adjacent to the main circuit block. Protective elements are connected between the first and second ground lines so as to form short circuits through at least one of the first and second ground lines.

Abstract: A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition.