Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.

Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.

Abstract: This invention provides a semiconductor device by which a high-speed DRAM cell and logic circuit can be obtained without increasing the number of fabrication steps, and a method of fabricating the same. A memory cell is constructed of capacitors formed in two end portions of an element formation region of a silicon substrate and a MOS transistor formed between these capacitors. The interval between gate electrodes of MOS transistors in adjacent memory cells is made larger than the intervals between these gate electrodes and gate electrodes formed outside the former gate electrodes. A portion above an n-type diffusion layer connected to a capacitor node is filled with a spacer insulating film, and an n-type diffusion layer connected to a bit line is covered with the spacer insulating film. A titanium silicide film is formed on one of these n-type diffusion layers and the gate electrodes.

Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.

Abstract: Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.

Abstract: A manufacturing method of semiconductor devices and semiconductor devices isolated by a trench portion. The trench portion is refilled with a Si epitaxial growth layer. The trench has a first insulating layer on its side wall and a second insulating layer formed by the oxidation in the self-alignment manner, as a cap layer, on the top portion of the trench. A semiconductor device formed on the substrate is isolated by the trench. The excessive leakage currents created by the stress between the substrate and the Si epitaxial layer are decreased. The concentration of the field effect at the corner portion of the trench is suppressed by the cap layer.The refilling step can be also made to a trench having the wider opening and another trench having the narrower opening simultaneously and uniformly.

Abstract: Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.

Abstract: A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

Abstract: A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

Abstract: In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.

Abstract: A semiconductor device of this invention includes a semiconductor substrate, at least one memory cell section including a number of memory cells each formed of a capacitor and a MOS transistor formed on the semiconductor substrate, a peripheral circuit section formed on the semiconductor substrate in an area other than an area in which the memory cell section is formed, and a wiring layer serving as an upper electrode of the capacitor and serving as a wire of the peripheral circuit section.

Abstract: A manufacturing method of semiconductor devices and semiconductor devices isolated by a trench portion. The trench portion is refilled with a Si epitaxial growth layer. The trench has a first insulating layer on its side wall and a second insulating layer formed by the oxidation in the self-alignment manner, as a cap layer, on the top portion of the trench. A semiconductor device formed on the substrate is isolated by the trench. The excessive leakage currents created by the stress between the substrate and the Si epitaxial layer are decreased. The concentration of the field effect at the corner portion of the trench is suppressed by the cap layer. The refilling step can be also made to a trench having the wider opening and another trench having the narrower opening simultaneously and uniformly.

Abstract: A semiconductor device has a semiconductor substrate of the first conductivity type, a gate electrode buried in a groove formed in an element region of the substrate, first source and drain regions of the second conductivity type formed in surface regions of the semiconductor substrate on either side of the gate electrode, and second source and drain regions each having a concentration higher than that of each of the first source and drain regions, the second source and drain regions being formed in the surface regions of the semiconductor substrate on either side of the gate electrode, spaced away from the gate electrode, and adjacent to the first source and drain regions, respectively. This semiconductor device has a structure wherein the gate electrode is deeply buried in the substrate. Therefore, a short channel effect can be prevented.

Abstract: A MOS-type semiconductor integrated circuit device is provided in which MOS transistors are formed in a vertical configuration. The MOS transistors are constituted by pillar layers formed on the substrate. The outer circumferential surfaces of the pillar layers are utilized to form the gates of the MOS transistors. Thus, large gate widths thereof can be obtained within a small area. As a result, the total chip area of the MOS transistors can be significantly reduced while maintaining a prescribed current-carrying capacity.

Abstract: A high integration semiconductor device comprises a semiconductor substrate and element separating regions formed on the semiconductor substrate to divide the semiconductor substrate into a plurality of regions to be formed as semiconductor active regions. The semiconductor active regions have contact portions for conducting the semiconductor active regions to other portions. The element separating regions are so constituted that the width of a short side of each of the semiconductor active regions at each contact portion is narrower than the width of a short side of the other portion of the semiconductor active region.

Abstract: A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array.

Abstract: A P channel MIS type semiconductor device have P type source and drain regions formed in a N type semiconductor substrate. Each source and drain regions are constructed the low and high impurity concentration layers. Channel side edges of the low concentration impurity layers arranged inside of the high concentration impurity layers. These double layer source and drain structure prevent the off set gate construction and the parasitic resistance.

Abstract: A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array.