Abstract: An echo canceller which cancels an echo by generating a replica of echo from the transmit data when the signal from the transmit line appears as an echo signal on the receive line, and subtracting the replica of echo from the echo signal in a circuit for connecting a transmit line and receive line to the full duplex transmission line through a hybrid circuit. The echo canceller for generating a replica of echo is composed of the first circuit which generates a replica of echo of limited length and a second circuit in which generates a replica of echo for eliminating the residual echo that is not cancelled by the first circuit.

Abstract: A pulse generating circuit is provided for generating a pulse having a time width synchronized with an input pulse and corresponding to a reference voltage. The circuit is particularly designed not to be affected by parasitic capacitance. A circuit for charging one electrode of an integrating circuit with a constant current is controlled by turning on or off a switch in response to the input pulse. The other electrode of the integrating capacitor is connected with a reference voltage source by driving a switch in response to a pulse having a pulse width which contains the time period of the input pulse and which is wider than the input pulse. A comparator is provided for comparing the potential at one electrode of the integrating capacitor and ground potential. A desired pulse is generated by a logic circuit which is receives both the output of the comparator and the input pulse.

Abstract: A method and a system for bidirectional transmission/reception of data between two terminal stations, in which each transmission period is divided into a plurality of first time sections for relatively low speed data transmission and at least one second time section for relatively high speed data transmission, the direction of transmission between the terminal stations being predetermined in each of the first time sections, while the direction of transmission between the terminal stations is reversible in each of the second time sections, each second time section being preceded by one of the first time sections. Transmission of information data and control data is performed from one to the other terminal station in a predetermined direction in each first time section, and the direction of data transmission between the terminal stations in the next second time section is determined on the basis of control data contained in the relatively low speed data transmission.

Abstract: A switched-capacitor filter of the present invention constituted in the form of a semiconductor integrated circuit has an input circuit which consists of at least one noninversion-type switched-capacitor and at least two inversion-type switched-capacitors that are connected in parallel with each other. The two inversion-type switched-capacitors have different writing timings and reading timings relative to each other. With this setup, capacitances of the switched-capacitors need not be extremely increased even when it is desired to maintain a zero-point frequency of the filter at a very low value. Further, there is no need of providing a circuit such as sample holding circuit which requires extra area and consumes additional electric power.

Abstract: A line equalizer for eliminating a precursor interference component and postcursor interference components from a pulse signal inputted from a transmission line. A precursor equalizer takes a sum of a signal derived from the input pulse signal retarded by a fundamental period and a signal derived from the input pulse signal multiplied by a coefficient a. A decision circuit decides the threshold level of an output pulse signal from the precursor equalizer to output a predetermined signal. A controller controls the coefficient a of the precursor equalizer on the basis of the signal from the decision circuit, etc.

Abstract: In a waveform differential type timing phase detector circuit, phase information available from the timing phase detector circuit is made valid for use as control information only when the input pulse assumes a specified pattern, in order to detect a timing phase signal removal of jitters due to waveform distortion.

Abstract: A switched-capacitor filter constituted in the form of a semiconductor integrated circuit has an input circuit which consists of at least one noninversion-type switched-capacitor and at least two inversion-type switched-capacitors that are connected in parallel with each other. The two inversion-type switched-capacitors have different writing timings and reading timings relative to each other. With this setup, capacitances of the switched-capacitors need not be extremely increased even when it is desired to maintain a zero-point frequency of the filter at a very low value. Further, there is no need of providing a circuit such as sample holding circuit which requires extra area and consumes additional electric power.

Abstract: A timing signal extraction circuit has a clock signal extractor for extracting from a transmitted data signal a clock component synchronous with the transmission rate of the transmitted signal, an oscillator having an oscillation frequency about M (M: an integer) times as high as the transmission rate of the transmitted signal, a phase-locked loop detecting the phase difference between the output signal of a frequency divider frequency-dividing the output signal of the oscillator and the output signal of the clock signal extractor thereby controlling the operating phase of the oscillator, and a logic circuit producing a plurality of pulse trains whose bit rate is equal to the transmission rate of the transmitted signal and which have respectively different phases. A pulse train having a desired phase is selected from among the plural pulse trains to provide a decision timing signal.

Abstract: A line equalizer including a .sqroot.f equalizer for compensating a .sqroot.f-characteristic of a transmission line, a BT equalizer connected in series with the .sqroot.f equalizer for removing an echo component caused by a bridged tap (namely, BT) on the transmission line, and a circuit for controlling the .sqroot.f equalizer is disclosed. A signal applied to the .sqroot.f equalizer is subjected to over-equalization to make the time domain length of impulse response at the output of the .sqroot.f equalizer small. The equalization state of the output of the .sqroot.f equalizer is judged by signals formed in the BT equalizer, and the gain of the .sqroot.f equalizer is controlled on the basis of the result of judgement. In this manner, the .sqroot.f equalizer is controlled without suffering any interference between a control loop of the .sqroot.f equalizer and a control loop of the BT equalizer.

Abstract: A small-sized LSI variable equalizer is provided for accurately equalizing waveforms of signals transmitted via transmission lines of different distances. Variable equalizer units capable of stepwise changing the equalizing characteristics thereof are connected in series with each other with the variable equalizer units having variable step widths different from each other. An output signal of the variable equalizer units is compared with a reference signal to convert the comparison output signal to a digital signal which includes an upper order bits and lower order bits, whereby one of the equalizer units which has a wide variable step width is controlled by the upper order bits and the other of the equalizer units which has a narrow variable step width is controlled by the lower order bits.